In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v4:
- Take Romain suggest, rebase on linux
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
- Take Romain suggest, rebase on linux-next branch
Signed-off-by: Yakir Yang
---
Changes in v4: None
Changes in v3: None
Changes in v2:
- Take J
method,
and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable m
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
- Take Romain suggest, rebase on linux-next branch
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4: None
Changes in v3: No
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Romain s
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Jingoo Han suggest, update commit message more readable.
- Adjust the order from 05 to 04
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property
() in to achieve the compatibility hacks.
Signed-off-by: Yakir Yang <y...@rock-chips.com>
---
Changes in v4:
- Take Krzysztof suggest, provide backword compatibility with samsung.
- Take Thierry suggest, add "color-depth" and "color-space" dynamic parsed.
Changes in
method,
and create devicetree binding for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable m
/next/linux-next.git when I'm preparing v4 series.
Thanks,
- Yakir
Regards,
Romain
2015-08-21 15:16 GMT+02:00 Thierry Reding :
On Fri, Aug 21, 2015 at 08:24:16PM +0900, Jingoo Han wrote:
On 2015. 8. 21., at PM 7:01, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/21 16:20, Jingoo Han 写道:
On 2015. 8. 19
/next/linux-next.git when I'm preparing v4 series.
Thanks,
- Yakir
Regards,
Romain
2015-08-21 15:16 GMT+02:00 Thierry Reding tred...@nvidia.com:
On Fri, Aug 21, 2015 at 08:24:16PM +0900, Jingoo Han wrote:
On 2015. 8. 21., at PM 7:01, Yakir Yang y...@rock-chips.com wrote:
Hi Jingoo,
在 2015/8/21
Hi Thierry,
在 2015/8/25 22:16, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry & Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT
Hi Thierry,
在 2015/8/25 18:06, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote
Hi Thierry,
在 2015/8/25 17:15, Thierry Reding 写道:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller
Hi Thierry,
在 2015/8/25 17:58, Thierry Reding 写道:
On Wed, Aug 19, 2015 at 09:50:34AM -0500, Yakir Yang wrote:
[...]
+ -analogix,color-space:
+ input video data format.
+ COLOR_RGB = 0, COLOR_YCBCR422 = 1, COLOR_YCBCR444 = 2
I don't think DT
Hi Thierry,
在 2015/8/25 22:16, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 09:48:01PM +0800, Yakir Yang wrote:
Hi Thierry Rob,
在 2015/8/25 21:27, Rob Herring 写道:
On Tue, Aug 25, 2015 at 4:15 AM, Thierry Reding tred...@nvidia.com wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring
Hi Thierry,
在 2015/8/25 18:06, Thierry Reding 写道:
On Tue, Aug 25, 2015 at 05:41:19PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/25 17:12, Thierry Reding 写道:
On Mon, Aug 24, 2015 at 09:48:27AM -0500, Rob Herring wrote:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li
, Yakir Yang y...@rock-chips.com wrote:
+ -analogix,color-depth:
+ number of bits per colour component.
+ COLOR_6 = 0, COLOR_8 = 1, COLOR_10 = 2, COLOR_12 = 3
This seems pretty generic. Just use 6, 8, 10, or 12 for values. And
drop the vendor prefix
Hi Thierry,
在 2015/8/25 17:15, Thierry Reding 写道:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
[...]
+ -analogix,link-rate:
+ max link rate supported by the eDP controller
Hi Heiko,
在 2015/8/24 21:03, Heiko Stuebner 写道:
Hi Yakir,
Am Montag, 24. August 2015, 20:48:01 schrieb Yakir Yang:
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00
Hi Krzysztof,
在 2015/8/25 7:49, Krzysztof Kozlowski 写道:
On 24.08.2015 21:48, Yakir Yang wrote:
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob
在 2015/8/24 22:48, Rob Herring 写道:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
+ -analogix,color-depth:
+ number of bits per colour
Hi Jingoo,
在 08/24/2015 03:40 PM, Jingoo Han 写道:
On 2015. 8. 24., at AM 9:43, Krzysztof Kozlowski
wrote:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from
Hi Jingoo,
在 08/24/2015 03:40 PM, Jingoo Han 写道:
On 2015. 8. 24., at AM 9:43, Krzysztof Kozlowski k.kozlow...@samsung.com
wrote:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote
在 2015/8/24 22:48, Rob Herring 写道:
On Mon, Aug 24, 2015 at 7:57 AM, Russell King - ARM Linux
li...@arm.linux.org.uk wrote:
On Sun, Aug 23, 2015 at 06:23:14PM -0500, Rob Herring wrote:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
+ -analogix,color-depth
Hi Heiko,
在 2015/8/24 21:03, Heiko Stuebner 写道:
Hi Yakir,
Am Montag, 24. August 2015, 20:48:01 schrieb Yakir Yang:
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00
Hi Krzysztof,
在 2015/8/25 7:49, Krzysztof Kozlowski 写道:
On 24.08.2015 21:48, Yakir Yang wrote:
Hi Krzysztof,
在 08/24/2015 12:20 PM, Krzysztof Kozlowski 写道:
On 24.08.2015 11:42, Yakir Yang wrote:
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring :
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update
Hi Rob,
在 08/23/2015 06:23 PM, Rob Herring 写道:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according
Hi Krzysztof,
在 08/23/2015 07:43 PM, Krzysztof Kozlowski 写道:
2015-08-24 8:23 GMT+09:00 Rob Herring robherri...@gmail.com:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt
Hi Rob,
在 08/23/2015 06:23 PM, Rob Herring 写道:
On Wed, Aug 19, 2015 at 9:50 AM, Yakir Yang y...@rock-chips.com wrote:
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file
Hi Ravi,
I'm wondering is your e-mail come from eDP thread ? cause I see lots of
cc guys some as eDP emails :)
And for your question, I am not sure I understand rightly. Do you mean
that your ".ko" module not in
the same directory with driver source code?
If it's your question, I think you
Hi Jingoo,
On 08/20/2015 02:49 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang wrote:
What is the reason to make this patch?
Please make commit message including the reason.
Okay, I think the below words would be okay :)
"This change just make a little clean to make
Hi Jingoo,
On 08/20/2015 02:22 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:50, Yakir Yang wrote:
link_rate and lane_count already configed in analogix_dp_set_link_train(),
s/configed/configured
Also, the commit name such as "fix ... bug" is not good.
How about following?
d
Hi Jingoo,
On 08/20/2015 01:55 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 3:23, Yakir Yang wrote:
Hi Jingoo & Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Sam
Hi Jingoo,
On 08/20/2015 01:11 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang wrote:
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
Hi Jingoo & Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can b
Hi Jingoo,
On 08/20/2015 02:22 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:50, Yakir Yang y...@rock-chips.com wrote:
link_rate and lane_count already configed in analogix_dp_set_link_train(),
s/configed/configured
Also, the commit name such as fix ... bug is not good.
How about following
Hi Jingoo,
On 08/20/2015 01:55 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 3:23, Yakir Yang y...@rock-chips.com wrote:
Hi Jingoo Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja arch...@codeaurora.org wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir
Hi Jingoo,
On 08/20/2015 02:49 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang y...@rock-chips.com wrote:
What is the reason to make this patch?
Please make commit message including the reason.
Okay, I think the below words would be okay :)
This change just make a little
Hi Jingoo,
On 08/20/2015 01:11 AM, Jingoo Han wrote:
On 2015. 8. 19., at PM 11:52, Yakir Yang y...@rock-chips.com wrote:
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works
Hi Jingoo Archit,
On 08/20/2015 12:54 AM, Jingoo Han wrote:
On 2015. 8. 20., at PM 1:29, Archit Taneja arch...@codeaurora.org wrote:
Hi,
On 08/19/2015 08:18 PM, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot
Hi Ravi,
I'm wondering is your e-mail come from eDP thread ? cause I see lots of
cc guys some as eDP emails :)
And for your question, I am not sure I understand rightly. Do you mean
that your .ko module not in
the same directory with driver source code?
If it's your question, I think you
Hi Dave,
On 08/19/2015 06:54 PM, Dave Airlie wrote:
On 20 August 2015 at 00:48, Yakir Yang wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge directory, then rk3288
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave "sclk_edp_24m" to rockchip
dp phy dr
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add edid modes parse support
Changes in v2: None
drivers/gpu/drm
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2: None
drivers/gpu/drm
Signed-off-by: Yakir Yang
---
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge/analogix_dp_core.c
b/drivers
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
"analogix,need-force-hpd" to indicate this sutiation.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Add "anal
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 26 +++
drivers/phy/Kconfig| 7 +
drivers/phy
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Heiko
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly, but we can take those as hardware limite.
For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps/lane,
so DT
-by: Yakir Yang
---
Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
struct drm_display_mode and struct drm_display_info.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 50 --
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 65
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Jingoo Han
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang
---
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid
for driver.
- Remove the clock enable/disbale with "sclk_edp" & "sclk_edp_24m",
leave those clock to rockchip dp phy driver.
- Add GNU license v2 declared and samsung copyright
- Fix compile failed dut to phy_pd_addr variable misspell error
Yakir Yang (14):
drm: exynos/d
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding and Heiko suggest, leave sclk_edp_24m to rockchip
dp
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h
, 2.7Gbps, 5.4Gbps}.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding suggest, link_rate and lane_count shouldn't config to
the DT property value directly, but we can take those as hardware limite.
For example, RK3288 only support 4 physical lanes of 2.7/1.62 Gbps
Analogix dp driver is split from exynos dp driver, so we just
make an copy of exynos_dp.txt, and then simplify exynos_dp.txt
Beside update some exynos dtsi file with the latest change
according to the devicetree binding documents.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Heiko suggest, add rockchip dp phy driver,
collect the phy clocks and power control.
Changes in v2: None
.../devicetree/bindings/phy/rockchip-dp-phy.txt| 26 +++
drivers/phy/Kconfig
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2
After run checkpatch.pl -f --subjective command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid
-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Take Thierry Reding suggest, dynamic parse video timing info from
struct drm_display_mode and struct drm_display_info.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 50 --
drivers/gpu/drm/exynos/analogix_dp
- Fix compile failed dut to phy_pd_addr variable misspell error
Yakir Yang (14):
drm: exynos/dp: fix code style
drm: exynos/dp: convert to drm bridge mode
drm: bridge: analogix_dp: split exynos dp driver to bridge dir
drm: bridge/analogix_dp: dynamic parse sync_pol interlace
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
This is an hardware property, so we need add a devicetree property
analogix,need-force-hpd to indicate this sutiation.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Add
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- move dp hpd detect to connector detect function.
Changes in v2: None
drivers/gpu/drm/bridge/analogix_dp_core.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/bridge
Display Port monitor could support kinds of mode which indicate
in monitor edid, not just one single display resolution which
defined in panel or devivetree property display timing.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3:
- Add edid modes parse support
Changes in v2
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v3: None
Changes in v2: None
Hi Dave,
On 08/19/2015 06:54 PM, Dave Airlie wrote:
On 20 August 2015 at 00:48, Yakir Yang y...@rock-chips.com wrote:
Hi all,
The Samsung Exynos eDP controller and Rockchip RK3288 eDP controller
share the same IP, so a lot of parts can be re-used. I split the common
code into bridge
Hi Russell,
在 2015/8/10 23:48, Russell King - ARM Linux 写道:
On Sat, Aug 08, 2015 at 05:10:47PM +0100, Russell King wrote:
From: Yakir Yang
Add ALSA based HDMI I2S audio driver for dw_hdmi. Sound card
driver could connect to this codec through the codec dai name
"dw-hdmi-i2s-audio"
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp->dev;
+ struct device_node *np = dev->of_node;
+ int ret;
+
+
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = <0>;
vsync-active-high = <0>;
interlaced = <0>
Hi Russell,
在 2015/8/10 23:48, Russell King - ARM Linux 写道:
On Sat, Aug 08, 2015 at 05:10:47PM +0100, Russell King wrote:
From: Yakir Yang y...@rock-chips.com
Add ALSA based HDMI I2S audio driver for dw_hdmi. Sound card
driver could connect to this codec through the codec dai name
dw-hdmi-i2s
Hi Thierry,
在 2015/8/10 21:17, Thierry Reding 写道:
On Mon, Aug 10, 2015 at 08:59:44PM +0800, Yakir Yang wrote:
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync
Hi Thierry,
在 2015/8/10 18:00, Thierry Reding 写道:
On Sat, Aug 08, 2015 at 11:54:38AM +0800, Yakir Yang wrote:
[...]
edp: edp@ff97 {
[...]
hsync-active-high = 0;
vsync-active-high = 0;
interlaced = 0;
These look like they should
Hi Heiko,
在 2015/8/10 20:08, Heiko Stübner 写道:
Hi Yakir,
Am Samstag, 8. August 2015, 11:54:38 schrieb Yakir Yang:
+static int rockchip_dp_init(struct rockchip_dp_device *dp)
+{
+ struct device *dev = dp-dev;
+ struct device_node *np = dev-of_node;
+ int ret;
+
+ dp-grf
still trying to integrate this into my development-tree.
Am Freitag, 7. August 2015, 05:46:20 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
Daniel,
在 2015/8/7 19:25, Daniel Vetter 写道:
On Thu, Aug 06, 2015 at 10:29:29PM +0800, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/6 22:19, Jingoo Han 写道:
On Thursday, August 06, 2015 11:07 PM, Yakir Yang wrote:
In order to move exynos dp code to bridge directory,
we need to convert driver drm
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
Signed-off-by: Yakir Yang
---
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
3 files changed
Some edp screen with no hpd signal would need some delay time
to ensure that screen would be ready for work, so we can expand
the delay time in hpd detect function, it works prefectly on my
rk3288 sdk board.
Signed-off-by: Yakir Yang
---
Changes in v2: None
drivers/gpu/drm/bridge
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang
---
Changes in v2: None
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang
---
Changes in v2: None
drivers/gpu/drm/rockchip/Kconfig| 10 +
drivers/gpu/drm/rockchip/Makefile
In order to move exynos dp code to bridge directory,
we need to convert driver drm bridge mode first. As
dp driver already have a ptn3460 bridge, so we need
to move ptn bridge to the next bridge of dp bridge.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Take Jingoo Han suggest, cause I jsut
After run "checkpatch.pl -f --subjective" command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang
---
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid using some uncommon style l
ight
- Fix compile failed dut to phy_pd_addr variable misspell error
Yakir Yang (8):
drm: exynos/dp: fix code style
drm: exynos/dp: convert to drm bridge mode
drm: bridge: analogix_dp: split exynos dp driver to bridge dir
drm: rockchip/dp: add rockchip platform dp driver
drm: bridge/analog
still trying to integrate this into my development-tree.
Am Freitag, 7. August 2015, 05:46:20 schrieb Yakir Yang:
Rockchip have three clocks for dp controller, we leave pclk_edp
to analogix_dp driver control, and keep the sclk_edp_24m and
sclk_edp in platform driver.
Signed-off-by: Yakir Yang y
Daniel,
在 2015/8/7 19:25, Daniel Vetter 写道:
On Thu, Aug 06, 2015 at 10:29:29PM +0800, Yakir Yang wrote:
Hi Jingoo,
在 2015/8/6 22:19, Jingoo Han 写道:
On Thursday, August 06, 2015 11:07 PM, Yakir Yang wrote:
In order to move exynos dp code to bridge directory,
we need to convert driver drm
After run checkpatch.pl -f --subjective command, I see there
are lots of alignment problem in exynos_dp driver, so let just
fix them.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Take Joe Preches advise, improved commit message more readable, and
avoid using some uncommon
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Add GNU license v2 declared and samsung copyright
drivers/gpu/drm/exynos/analogix_dp-exynos.c | 1 +
drivers/gpu/drm/rockchip/analogix_dp-rockchip.c | 1 +
include/drm/bridge/analogix_dp.h| 16
Some edp screen do not have hpd signal, so we can't just return
failed when hpd plug in detect failed.
Besides TRM indicate that if HPD_STATUS(RO) is 0, AUX CH will not
work, so we need to give a force hpd action to set HPD_STATUS manually.
Signed-off-by: Yakir Yang y...@rock-chips.com
RK3288 need some special registers setting, we can separate
them out by the dev_type of plat_data.
Signed-off-by: Yakir Yang y...@rock-chips.com
---
Changes in v2:
- Fix compile failed dut to phy_pd_addr variable misspell error
drivers/gpu/drm/bridge/analogix_dp_reg.c | 76
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