[PATCH 1/3] dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller

Add DT bindings for the Meson-AXG SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Yixun Lan <yixun@amlogic.com> --- .../bindings/reset/amlogic,meson-reset.txt | 3 +- .../dt-bindings/reset/amlogic,meson-axg-reset.h

[PATCH 1/3] dt-bindings: reset: Add bindings for the Meson-AXG SoC Reset Controller

Add DT bindings for the Meson-AXG SoC Reset Controller include file, and also slightly update documentation. Signed-off-by: Yixun Lan --- .../bindings/reset/amlogic,meson-reset.txt | 3 +- .../dt-bindings/reset/amlogic,meson-axg-reset.h| 124 + 2 files changed

[PATCH 1/4] documentation: Add compatibles for Amlogic Meson AXG pin controllers

From: Xingyu Chen <xingyu.c...@amlogic.com> Add compatibles for Amlogic Meson AXG pin controllers Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 ++

[PATCH 4/4] ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC

From: Xingyu Chen <xingyu.c...@amlogic.com> Add new pinctrl DT info for the Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 43

[PATCH 1/4] documentation: Add compatibles for Amlogic Meson AXG pin controllers

From: Xingyu Chen Add compatibles for Amlogic Meson AXG pin controllers Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/pinctrl/meson,pinctrl.txt | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/pinctrl/meson

[PATCH 4/4] ARM64: dts: meson-axg: add pinctrl DT info for Meson-AXG SoC

From: Xingyu Chen Add new pinctrl DT info for the Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- arch/arm64/boot/dts/amlogic/meson-axg.dtsi | 43 ++ 1 file changed, 43 insertions(+) diff --git a/arch/arm64/boot/dts/amlogic/meson

[PATCH 3/4] pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC

From: Xingyu Chen <xingyu.c...@amlogic.com> Add new pinctrl driver for Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/pinctrl/meson/Kconfig | 6 + drivers/pinc

[PATCH 2/4] pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC

-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/pinctrl/meson/Kconfig | 3 + drivers/pinctrl/meson/Makefile| 1 + drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c | 118 ++ d

[PATCH 3/4] pinctrl: meson-axg: Add new pinctrl driver for Meson AXG SoC

From: Xingyu Chen Add new pinctrl driver for Amlogic's Meson-AXG SoC. Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- drivers/pinctrl/meson/Kconfig | 6 + drivers/pinctrl/meson/Makefile| 1 + drivers/pinctrl/meson/pinctrl-meson-axg.c | 976

[PATCH 2/4] pinctrl: meson-axg: Introduce a pinctrl pinmux ops for Meson-AXG SoC

From: Xingyu Chen The pin controller has been updated in the Amlogic Meson AXG series, which use continuous 4-bit register to select function for each pin. In order to support this, a new pinmux operations "meson_axg_pmx_ops" has been added. Signed-off-by: Xingyu Chen Signed-off-by:

[PATCH 0/4] add pinctrl driver for Meson-AXG SoC

patch [1/4]: Document the new pinctrl compatible string for Meson-AXG patch [2/4]: Introduce a new pinctrl pinmux ops for Meson-AXG SoC. The pinctrl IP has been changed, and now it use 4-bit continuous bit to decribe the pin. patch [3/4]: Add pinctrl driver

[PATCH 0/4] add pinctrl driver for Meson-AXG SoC

patch [1/4]: Document the new pinctrl compatible string for Meson-AXG patch [2/4]: Introduce a new pinctrl pinmux ops for Meson-AXG SoC. The pinctrl IP has been changed, and now it use 4-bit continuous bit to decribe the pin. patch [3/4]: Add pinctrl driver

[PATCH v4 1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA

v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) di

[PATCH v4 1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA

v0.3_20170314 Fixes: 738f66d3211d ("clk: gxbb: add AmLogic GXBB clk controller driver") Tested-by: Xingyu Chen Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gx

[PATCH v4 4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC

From: Xingyu Chen <xingyu.c...@amlogic.com> The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- ar

[PATCH v4 4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC

From: Xingyu Chen The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- arch/arm/boot/dts/meson8b.dtsi | 5 ++--- arch/arm64/boot/dts/amlogic/meson-gxb

[PATCH v4 3/4] dt-bindings: iio: adc: update the doc for SAR ADC

From: Xingyu Chen <xingyu.c...@amlogic.com> Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/iio/adc/amlog

[PATCH v4 3/4] dt-bindings: iio: adc: update the doc for SAR ADC

From: Xingyu Chen Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/

[PATCH v4 2/4] iio: adc: meson-saradc: remove irrelevant clock "sana"

From: Xingyu Chen <xingyu.c...@amlogic.com> The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC, it is irrelevant for the SAR ADC. Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers

[PATCH v4 2/4] iio: adc: meson-saradc: remove irrelevant clock "sana"

From: Xingyu Chen The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC, it is irrelevant for the SAR ADC. Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- drivers/iio/adc/meson_saradc.c | 20 1 file changed, 20 deletions(-) diff --git a/d

[PATCH v4 0/4] fix the clock setting for SAR ADC

0170314publicversion-Wesion.pdf Xingyu Chen (3): iio: adc: meson-saradc: remove irrelevant clock "sana" dt-bindings: iio: adc: update the doc for SAR ADC ARM64: dts: meson: drop "sana" clock from SAR ADC Yixun Lan (1): clk: meson: gxbb: fix wrong clock for SARADC/S

[PATCH v4 0/4] fix the clock setting for SAR ADC

0170314publicversion-Wesion.pdf Xingyu Chen (3): iio: adc: meson-saradc: remove irrelevant clock "sana" dt-bindings: iio: adc: update the doc for SAR ADC ARM64: dts: meson: drop "sana" clock from SAR ADC Yixun Lan (1): clk: meson: gxbb: fix wrong clock for SARADC/S

Re: [PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SARADC

Hi On 11/07/17 13:37, Yixun Lan wrote: > From: Xingyu Chen <xingyu.c...@amlogic.com> > > The SAR ADC modules doesn't require The "sana" clock. > > Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> > Signed-off-by: Yixun Lan <yixun@amlogic.

Re: [PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SARADC

Hi On 11/07/17 13:37, Yixun Lan wrote: > From: Xingyu Chen > > The SAR ADC modules doesn't require The "sana" clock. > > Singed-off-by: Xingyu Chen > Signed-off-by: Yixun Lan > --- > arch/arm/boot/dts/meson8.dtsi | 5 ++--- > arch/arm/b

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Martin On 11/07/17 06:03, Martin Blumenstingl wrote: > Hi Yixun, > > On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan <yixun@amlogic.com> wrote: >> Hi Neil: >> >> >> On 11/06/17 16:57, Neil Armstrong wrote: >>> On 06/11/2017 08:52, Yixun Lan wrote

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Martin On 11/07/17 06:03, Martin Blumenstingl wrote: > Hi Yixun, > > On Mon, Nov 6, 2017 at 10:31 AM, Yixun Lan wrote: >> Hi Neil: >> >> >> On 11/06/17 16:57, Neil Armstrong wrote: >>> On 06/11/2017 08:52, Yixun Lan wrote: >>>>

[PATCH v3 1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA

ingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index b2d1e8ed7152..92168348ffa6 100644 --- a/dr

[PATCH v3 1/4] clk: meson: gxbb: fix wrong clock for SARADC/SANA

ingyu Chen Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/meson/gxbb.c b/drivers/clk/meson/gxbb.c index b2d1e8ed7152..92168348ffa6 100644 --- a/drivers/clk/meson/gxbb.c +++ b/drivers/clk/meson/gxbb.c @@ -1139

[PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SARADC

From: Xingyu Chen <xingyu.c...@amlogic.com> The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- ar

[PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SARADC

From: Xingyu Chen The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- arch/arm/boot/dts/meson8b.dtsi | 5 ++--- arch/arm64/boot/dts/amlogic/meson-gxb

[PATCH v3 2/4] iio: adc: meson-saradc: remove irrelevant clock "sana"

From: Xingyu Chen <xingyu.c...@amlogic.com> The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC, it is irrelevant for the SAR ADC. Signed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers

[PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC

From: Xingyu Chen <xingyu.c...@amlogic.com> The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- ar

[PATCH v3 2/4] iio: adc: meson-saradc: remove irrelevant clock "sana"

From: Xingyu Chen The "sana" clock is not used at SAR ADC module in Amlogic Meson SoC, it is irrelevant for the SAR ADC. Signed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- drivers/iio/adc/meson_saradc.c | 20 1 file changed, 20 deletions(-) diff --git a/d

[PATCH v3 4/4] ARM64: dts: meson: drop "sana" clock from SAR ADC

From: Xingyu Chen The SAR ADC modules doesn't require The "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- arch/arm/boot/dts/meson8.dtsi | 5 ++--- arch/arm/boot/dts/meson8b.dtsi | 5 ++--- arch/arm64/boot/dts/amlogic/meson-gxb

[PATCH v3 3/4] dt-bindings: iio: adc: update the doc for SAR ADC

From: Xingyu Chen <xingyu.c...@amlogic.com> Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan <yixun@amlogic.com> --- Documentation/devicetree/bindings/iio/adc/amlog

[PATCH v3 3/4] dt-bindings: iio: adc: update the doc for SAR ADC

From: Xingyu Chen Update the doc as the SAR ADC modules doesn't require "sana" clock. Singed-off-by: Xingyu Chen Signed-off-by: Yixun Lan --- Documentation/devicetree/bindings/iio/adc/amlogic,meson-saradc.txt | 1 - 1 file changed, 1 deletion(-) diff --git a/Documentation/

[PATCH v3 0/4] fix the clock setting for SAR ADC

radead.org/pipermail/linux-amlogic/2017-November/005242.html Xingyu Chen (3): iio: adc: meson-saradc: remove irrelevant clock "sana" dt-bindings: iio: adc: update the doc for SAR ADC ARM64: dts: meson: drop "sana" clock from SAR ADC Yixun Lan (1): clk: meson: gxbb: fix wr

[PATCH v3 0/4] fix the clock setting for SAR ADC

radead.org/pipermail/linux-amlogic/2017-November/005242.html Xingyu Chen (3): iio: adc: meson-saradc: remove irrelevant clock "sana" dt-bindings: iio: adc: update the doc for SAR ADC ARM64: dts: meson: drop "sana" clock from SAR ADC Yixun Lan (1): clk: meson: gxbb: fix wr

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Jerome: On 11/06/17 17:10, Jerome Brunet wrote: > On Mon, 2017-11-06 at 15:52 +0800, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Neil: On 11/06/17 16:57, Neil Armstrong wrote: > On 06/11/2017 08:52, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >>

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

Hi Neil: On 11/06/17 16:57, Neil Armstrong wrote: > On 06/11/2017 08:52, Yixun Lan wrote: >> According to the datasheet, in Meson-GXBB/GXL series, >> The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], >> while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. >>

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl_skt dev board. Tested-by: Xingyu Chen <xingyu.c...@amlogic.com> Signed-off-by: Yixun Lan

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC/SANA

According to the datasheet, in Meson-GXBB/GXL series, The clock gate bit for SARADC is HHI_GCLK_MPEG2 bit[22], while clock gate bit for SANA is HHI_GCLK_MPEG0 bit[10]. Test passed at gxl_skt dev board. Tested-by: Xingyu Chen Signed-off-by: Yixun Lan --- I think this error was introduced

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

Hi Neil On 11/05/17 00:40, Neil Armstrong wrote: > Hi Yixun, > > Le 04/11/2017 09:41, Yixun Lan a écrit : >> >> >> On 11/04/17 02:17, Yixun Lan wrote: >>> According to the datasheet, the clock gate bit for >>> SARADC is bit[22

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

Hi Neil On 11/05/17 00:40, Neil Armstrong wrote: > Hi Yixun, > > Le 04/11/2017 09:41, Yixun Lan a écrit : >> >> >> On 11/04/17 02:17, Yixun Lan wrote: >>> According to the datasheet, the clock gate bit for >>> SARADC is bit[22

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

On 11/04/17 02:17, Yixun Lan wrote: > According to the datasheet, the clock gate bit for > SARADC is bit[22] in Meson-GXBB/GXL series. > > Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 > Signed-off-by: Yixun Lan <yixun@amlogic.com> > --- > drivers/clk/me

Re: [PATCH] clk: meson: gxbb: fix wrong clock for SARADC

On 11/04/17 02:17, Yixun Lan wrote: > According to the datasheet, the clock gate bit for > SARADC is bit[22] in Meson-GXBB/GXL series. > > Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 > Signed-off-by: Yixun Lan > --- > drivers/clk/meson/gxbb.c | 2 +- > 1 f

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC

According to the datasheet, the clock gate bit for SARADC is bit[22] in Meson-GXBB/GXL series. Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 Signed-off-by: Yixun Lan <yixun@amlogic.com> --- drivers/clk/meson/gxbb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff

[PATCH] clk: meson: gxbb: fix wrong clock for SARADC

According to the datasheet, the clock gate bit for SARADC is bit[22] in Meson-GXBB/GXL series. Change-Id: Ic4fa58276d2a9ea273eef0a08541fc213ac5ac89 Signed-off-by: Yixun Lan --- drivers/clk/meson/gxbb.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/meson/gxbb.c

Re: [PATCH v2] serial: meson: add Magic SysRq support

Hi Greg-KH I think you've already accepted this patch (and merged into your git repo) so, is it possible for you to amend the commit message? or do you want me to send a PATCH v3 then? On 10:10 Fri 20 Oct , Neil Armstrong wrote: > Hi Yixun, > > On 06/09/2017 15:52, Yixun

Re: [PATCH v2] serial: meson: add Magic SysRq support

Hi Greg-KH I think you've already accepted this patch (and merged into your git repo) so, is it possible for you to amend the commit message? or do you want me to send a PATCH v3 then? On 10:10 Fri 20 Oct , Neil Armstrong wrote: > Hi Yixun, > > On 06/09/2017 15:52, Yixun

Re: [PATCH 1/2] pinctrl: meson: separate soc drivers

hi jerome: On Mon, Oct 9, 2017 at 7:35 PM, Neil Armstrong wrote: > On 09/10/2017 12:17, Jerome Brunet wrote: >> When meson pinctrl is enabled, all meson platforms pinctrl drivers are >> built in the kernel, with a significant amount of data. >> >> This leads to

Re: [PATCH 1/2] pinctrl: meson: separate soc drivers

hi jerome: On Mon, Oct 9, 2017 at 7:35 PM, Neil Armstrong wrote: > On 09/10/2017 12:17, Jerome Brunet wrote: >> When meson pinctrl is enabled, all meson platforms pinctrl drivers are >> built in the kernel, with a significant amount of data. >> >> This leads to situation where pinctrl drivers

[PATCH v2] serial: meson: add Magic SysRq support

s fine. [1] Documentation/admin-guide/sysrq.rst Signed-off-by: Yixun Lan <d...@gentoo.org> --- Changes since v1 at [0]: - add changelog & a few more comments [0] https://patchwork.kernel.org/patch/9728475/ --- drivers/tty/serial/meson_uart.c | 18 -- 1 file changed, 16 inser

[PATCH v2] serial: meson: add Magic SysRq support

s fine. [1] Documentation/admin-guide/sysrq.rst Signed-off-by: Yixun Lan --- Changes since v1 at [0]: - add changelog & a few more comments [0] https://patchwork.kernel.org/patch/9728475/ --- drivers/tty/serial/meson_uart.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions

[PATCH] serial: meson: add Magic SysRq support

Signed-off-by: Yixun Lan <d...@gentoo.org> --- drivers/tty/serial/meson_uart.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 60f16795d16b..f0d9222db82f 100644 --- a/drivers/tty/

[PATCH] serial: meson: add Magic SysRq support

Signed-off-by: Yixun Lan --- drivers/tty/serial/meson_uart.c | 18 -- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/drivers/tty/serial/meson_uart.c b/drivers/tty/serial/meson_uart.c index 60f16795d16b..f0d9222db82f 100644 --- a/drivers/tty/serial/meson_uart.c

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