Michael S. Tsirkin wrote on 2015-11-16:
> This patch adds a new parameter: eptp_switching_test, which enables
> testing EPT switching on VMX if supported by hardware. All EPT
> entries are initialized to the same value so this adds no useful
> functionality by itself, but can be used to test VMFUN
Paolo Bonzini wrote on 2015-11-13:
> Commit 7a1638ce4220 ("nEPT: Redefine EPT-specific link_shadow_page()",
> 2013-08-05) says:
>
> Since nEPT doesn't support A/D bit, we should not set those bit
> when building the shadow page table.
> but this is not necessary. Even though nEPT doesn't
Zhang, Yang Z wrote on 2015-08-04:
> Paolo Bonzini wrote on 2015-08-04:
>>
>>
>> On 04/08/2015 02:46, Zhang, Yang Z wrote:
>>>> It is a problem for split irqchip, where the EOI exit bitmap can
>>>> be inferred from the IOAPIC routes but the TMR can
Paolo Bonzini wrote on 2015-08-04:
>
>
> On 04/08/2015 02:46, Zhang, Yang Z wrote:
>>> It is a problem for split irqchip, where the EOI exit bitmap can be
>>> inferred from the IOAPIC routes but the TMR cannot. The hardware
>>> behavior on the other hand
Paolo Bonzini wrote on 2015-08-03:
>
>
> On 03/08/2015 12:23, Zhang, Yang Z wrote:
>>> In any case, the TMR behavior introduced by the APICv patches is
>>> completely different from the hardware behavior, so it has to be fixed.
>>
>> But any real problem
Paolo Bonzini wrote on 2015-08-03:
>
>
> On 03/08/2015 04:37, Zhang, Yang Z wrote:
>>>> Only virtualized APIC register reads use the virtual TMR
>>>> registers (SDM
>>>> 29.4.2 or 29.5), but these just read data from the corresponding
>>>>
Paolo Bonzini wrote on 2015-07-31:
>
>
> On 31/07/2015 04:49, Steve Rutherford wrote:
>> Oh... Yeah. That's a damn good point, given that the interrupt can be
>> injected from another thread while one is in that guest vcpu.
>>
>> Easiest time to update the TMR should be on guest entry through
>>
Paolo Bonzini wrote on 2015-07-31:
>
>
> On 31/07/2015 01:26, Zhang, Yang Z wrote:
>>>> Do not compute TMR in advance. Instead, set the TMR just before
>>>> the interrupt is accepted into the IRR. This limits the coupling
>>>> between IOAPIC an
Paolo Bonzini wrote on 2015-07-29:
> Do not compute TMR in advance. Instead, set the TMR just before the
> interrupt is accepted into the IRR. This limits the coupling between
> IOAPIC and LAPIC.
>
Uh.., it back to original way which is wrong. You cannot modify the apic
page(here is the TMR re
Paolo Bonzini wrote on 2015-05-20:
>
>
> On 20/05/2015 07:20, Zhang, Yang Z wrote:
>> Li, Liang Z wrote on 2015-05-20:
>>> The MPX feature requires eager KVM FPU restore support. We have
>>> verified that MPX cannot work correctly with the current lazy KVM
>
Li, Liang Z wrote on 2015-05-20:
> The MPX feature requires eager KVM FPU restore support. We have
> verified that MPX cannot work correctly with the current lazy KVM FPU
> restore mechanism. Eager KVM FPU restore should be enabled if the MPX
> feature is exposed to VM.
>
> Signed-off-by: Liang Li
Paolo Bonzini wrote on 2015-05-19:
>
>
> On 19/05/2015 16:25, Zhang, Yang Z wrote:
>> Paolo Bonzini wrote on 2015-04-30:
>>> This patch series introduces system management mode support.
>>
>> Just curious what's motivation to add vSMM supporting? Is ther
Paolo Bonzini wrote on 2015-04-30:
> This patch series introduces system management mode support.
Just curious what's motivation to add vSMM supporting? Is there any usage case
inside guest requires SMM? Thanks.
> There is still some work to do, namely: test without unrestricted
> guest support,
Paolo Bonzini wrote on 2015-04-24:
>
>
> On 24/04/2015 09:46, Zhang, Yang Z wrote:
>>> On the other hand vmexit is lighter and lighter on newer
>>> processors; a Sandy Bridge has less than half the vmexit cost of a
>>> Core 2 (IIRC
>>> 1000 vs.
Paolo Bonzini wrote on 2015-04-24:
>
>
> On 24/04/2015 03:16, Zhang, Yang Z wrote:
>>> This is interesting since previous measurements on KVM have had the
>>> exact opposite results. I think we need to understand this a lot
>>> more.
>>
>> W
H. Peter Anvin wrote on 2015-04-24:
> On 04/23/2015 08:28 AM, Dave Hansen wrote:
>> On 04/23/2015 02:13 PM, Liang Li wrote:
>>> When compiling kernel on westmere, the performance of eager FPU is
>>> about 0.4% faster than lazy FPU.
>>
>> Do you have an theory why this is? What does the regression
Paolo Bonzini wrote on 2015-02-03:
>
>
> On 02/02/2015 16:33, Wincy Van wrote:
>> static void vmx_accomp_nested_posted_intr(struct kvm_vcpu *vcpu) {
>> struct vcpu_vmx *vmx = to_vmx(vcpu);
>>
>> if (is_guest_mode(vcpu) &&
>> vmx->nested.posted_intr_nv != -1 &&
Wincy Van wrote on 2015-01-29:
> On Thu, Jan 29, 2015 at 10:54 AM, Zhang, Yang Z
> wrote:
>>> -8646,7 +8750,8 @@ static void prepare_vmcs02(struct kvm_vcpu
>>> *vcpu, struct vmcs12 *vmcs12)
>>> else
>>> vmcs_write64(A
Wincy Van wrote on 2015-01-28:
> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
> performance, especially in apicv case.
>
> This patch also introduces nested_vmx_check_apicv_controls for the nested
> apicv patches.
>
> Signed-off-by: Wincy Van
> ---
> arch/x86/kvm/vm
Wincy Van wrote on 2015-01-28:
> v1 ---> v2:
> Use spin lock to ensure vmcs12 is safe when doing nested
> posted interrupt delivery.
> v2 ---> v3:
> 1. Add a new field in nested_vmx to avoid the spin lock in v2.
> 2. Drop send eoi to L1 when doing nested interrupt delivery.
> 3. Use hardw
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 7:25 PM, Zhang, Yang Z
> wrote:
>> Wincy Van wrote on 2015-01-28:
>>> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
>>>
>>> wrote:
>>>>> @@ -8344,7 +8394,68 @@ static int
>>&g
Wincy Van wrote on 2015-01-24:
> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
> performance, especially in apicv case.
>
> This patch also introduces nested_vmx_check_apicv_controls for the nested
> apicv patches.
>
> Signed-off-by: Wincy Van
> ---
...snip...
> st
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 8:33 PM, Zhang, Yang Z
> wrote:
>>>>
>>>> You are right, but this is not fit for all the cases, we should
>>>> custom the nested_msr_bitmap.
>>>> e.g. Currently L0 wants to interc
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
> wrote:
>>>>
>>>
>>> If L0 wants to intercept a msr, we should set
>>> vmx_msr_bitmap_legacy(_x2apic) and vmx_msr_bitmap_longmode(_x2apic),
>>> and that bitmap
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 4:05 PM, Zhang, Yang Z
> wrote:
>>> @@ -8344,7 +8394,68 @@ static int
>>> nested_vmx_check_msr_bitmap_controls(struct kvm_vcpu *vcpu, static
>>> inline bool nested_vmx_merge
Zhang, Yang Z wrote on 2015-01-28:
> Wincy Van wrote on 2015-01-28:
>> On Wed, Jan 28, 2015 at 7:52 PM, Zhang, Yang Z
>>
>> wrote:
>>>>>
>>>>
>>>> If L0 wants to intercept a msr, we should set
>>>> vmx_msr_bitmap_legacy(_x2
Wincy Van wrote on 2015-01-28:
> On Wed, Jan 28, 2015 at 4:00 PM, Zhang, Yang Z
> wrote:
>>> @@ -5812,13 +5813,18 @@ static __init int hardware_setup(void)
>>> (unsigned long
>>> *)__get_free_page(GFP_KERNEL);
>>>
Wincy Van wrote on 2015-01-24:
> Currently, if L1 enables MSR_BITMAP, we will emulate this feature, all of L2's
> msr access is intercepted by L0. Since many features like virtualize x2apic
> mode
> has a complicated logic and it is difficult for us to emulate, we should use
> hardware and merge t
Zhang, Yang Z wrote on 2015-01-28:
> Wincy Van wrote on 2015-01-24:
>> When L2 is using x2apic, we can use virtualize x2apic mode to gain
>> higher performance, especially in apicv case.
>>
>> This patch also introduces nested_vmx_check_apicv_controls for the
>
Wincy Van wrote on 2015-01-21:
> On Wed, Jan 21, 2015 at 4:07 PM, Zhang, Yang Z
> wrote:
>>> + if (vector == vmcs12->posted_intr_nv && +
>>> nested_cpu_has_posted_intr(vmcs12)) { + if (vcpu->mode
>>> == IN_GUEST_MOD
Wincy Van wrote on 2015-01-16:
> When L2 is using x2apic, we can use virtualize x2apic mode to gain higher
> performance.
>
> This patch also introduces nested_vmx_check_apicv_controls for the nested
> apicv patches.
>
> Signed-off-by: Wincy Van
To enable x2apic, should you to consider the beha
Wincy Van wrote on 2015-01-16:
> To enable nested apicv support, we need per-cpu vmx control MSRs:
> 1. If in-kernel irqchip is enabled, we can enable nested
> posted interrupt, we should set posted intr bit in the
> nested_vmx_pinbased_ctls_high. 2. If in-kernel irqchip is disabled,
>
Wincy Van wrote on 2015-01-20:
> If vcpu has a interrupt in vmx non-root mode, we will kick that vcpu
> to inject interrupt timely. With posted interrupt processing, the kick
> intr is not needed, and interrupts are fully taken care of by hardware.
>
> In nested vmx, this feature avoids much more
Wincy Van wrote on 2015-01-20:
> Hi, Yang,
>
> Could you please have a look at this patch set?
> Your comment is very appreciated!
Sure. I will take a look.
>
>
> Thanks,
>
> Wincy
Best regards,
Yang
Wu, Feng wrote on 2014-12-24:
>
>
> Zhang, Yang Z wrote on 2014-12-24:
>> Cc: io...@lists.linux-foundation.org; linux-kernel@vger.kernel.org;
>> KVM list; Eric Auger
>> Subject: RE: [v3 06/26] iommu, x86: No need to migrating irq for
>> VT-d Posted-Interrupts
>
Jiang Liu wrote on 2014-12-24:
> On 2014/12/24 9:38, Zhang, Yang Z wrote:
>> Paolo Bonzini wrote on 2014-12-23:
>>>
>>>
>>> On 23/12/2014 10:07, Wu, Feng wrote:
>>>>> On 23/12/2014 01:37, Zhang, Yang Z wrote:
>>>>>> I don'
Paolo Bonzini wrote on 2014-12-23:
>
>
> On 23/12/2014 10:07, Wu, Feng wrote:
>>> On 23/12/2014 01:37, Zhang, Yang Z wrote:
>>>> I don't quite understand it. If user set an interrupt's affinity
>>>> to a CPU, but he still see the interrupt del
Paolo Bonzini wrote on 2014-12-23:
>> The problem is we still need to support PI with lowest priority
>> delivery mode
> even if guest does not configure irq affinity via /proc/irq/. Don't we?
>
> Yes, but we can get the basic support working first.
>
> I and Feng talked on irc and agreed to star
Paolo Bonzini wrote on 2014-12-19:
>
>
> On 19/12/2014 02:46, Zhang, Yang Z wrote:
>>> If the IRQ is posted, its affinity is controlled by guest (irq
>>> <---> vCPU <> pCPU), it has no effect when host changes its affinity.
>>
>> That'
Wu, Feng wrote on 2014-12-19:
>
>
> Zhang, Yang Z wrote on 2014-12-19:
>> Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
>> set
>>
>> Wu, Feng wrote on 2014-12-19:
>>>
>>>
>>> Zhang, Yang Z wrote on 2
Wu, Feng wrote on 2014-12-19:
>
>
> Zhang, Yang Z wrote on 2014-12-19:
>> Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
>> set
>>
>> Wu, Feng wrote on 2014-12-19:
>>>
>>>
>>> Zhang, Yang Z wrote on 2
Wu, Feng wrote on 2014-12-19:
>
>
> Zhang, Yang Z wrote on 2014-12-19:
>> Subject: RE: [v3 25/26] KVM: Suppress posted-interrupt when 'SN' is
>> set
>>
>> Wu, Feng wrote on 2014-12-19:
>>>
>>>
>>> iommu-boun...@l
Wu, Feng wrote on 2014-12-19:
>
>
> iommu-boun...@lists.linux-foundation.org wrote on
> mailto:iommu-boun...@lists.linux-foundation.org] On Behalf Of:
>> Cc: io...@lists.linux-foundation.org; linux-kernel@vger.kernel.org;
>> k...@vger.kernel.org
>> Subject: RE: [v3 25/26] KVM: Suppress posted-in
w interface
>> kvm_find_dest_vcpu() for VT-d PI
>>
>>
>>
>> On 18/12/2014 15:49, Zhang, Yang Z wrote:
>>>>> Here, we introduce a similar way with 'apic_arb_prio' to handle
>>>>> guest lowest priority interrtups when VT-d PI is us
Wu, Feng wrote on 2014-12-19:
>
>
> Zhang, Yang Z wrote on 2014-12-18:
>> jiang@linux.intel.com
>> Cc: eric.au...@linaro.org; linux-kernel@vger.kernel.org;
>> io...@lists.linux-foundation.org; k...@vger.kernel.org; Wu, Feng
>> Subject: RE: [v3 06/26] iommu,
Paolo Bonzini wrote on 2014-12-19:
>
>
> On 18/12/2014 15:49, Zhang, Yang Z wrote:
>>>> Here, we introduce a similar way with 'apic_arb_prio' to handle
>>>> guest lowest priority interrtups when VT-d PI is used. Here is the
>>>> ideas:
Feng Wu wrote on 2014-12-12:
> This patch initializes the VT-d Posted-Interrupts Descriptor.
>
> Signed-off-by: Feng Wu
> ---
> arch/x86/kvm/vmx.c | 27 +++
> 1 file changed, 27 insertions(+)
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c index
> 0b1383e..66ca275
Paolo Bonzini wrote on 2014-12-18:
>
>
> On 18/12/2014 04:14, Wu, Feng wrote:
>>
>>
>> linux-kernel-ow...@vger.kernel.org wrote on
>> mailto:linux-kernel-ow...@vger.kernel.org] On Behalf Of Paolo:
>>> x...@kernel.org; Gleb Natapov; Paolo Bonzini; dw...@infradead.org;
>>> joro-zlv9swrftaidnm+yr
Feng Wu wrote on 2014-12-12:
> Currently, we use a global vector as the Posted-Interrupts
> Notification Event for all the vCPUs in the system. We need to
> introduce another global vector for VT-d Posted-Interrtups, which will
> be used to wakeup the sleep vCPU when an external interrupt from a
>
Feng Wu wrote on 2014-12-12:
> This patch defines a new interface kvm_find_dest_vcpu for
> VT-d PI, which can returns the destination vCPU of the
> interrupt for guests.
>
> Since VT-d PI cannot handle broadcast/multicast interrupt,
> Here we only handle Fixed and Lowest priority interrupts.
>
>
Feng Wu wrote on 2014-12-12:
> We don't need to migrate the irqs for VT-d Posted-Interrupts here.
> When 'pst' is set in IRTE, the associated irq will be posted to guests
> instead of interrupt remapping. The destination of the interrupt is
> set in Posted-Interrupts Descriptor, and the migration h
Wu, Feng wrote on 2014-11-13:
>
>
> Zhang, Yang Z wrote on 2014-11-13:
>> k...@vger.kernel.org; io...@lists.linux-foundation.org;
>> linux-kernel@vger.kernel.org
>> Subject: RE: [PATCH 05/13] KVM: Update IRTE according to guest
>> interrupt configuration changes
Wu, Feng wrote on 2014-11-13:
>
>
> kvm-ow...@vger.kernel.org wrote on 2014-11-12:
>> k...@vger.kernel.org; io...@lists.linux-foundation.org;
>> linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH 05/13] KVM: Update IRTE according to guest
>> interrupt configuration changes
>>
>>
>>
>> On 12
Paolo Bonzini wrote on 2014-11-11:
>
>
> On 11/11/2014 10:20, Wu, Feng wrote:
>>> Since legacy KVM device assignment is effectively deprecated, have
>>> you considered how we might do this with VFIO? Thanks,
>>
>> I haven't thought about how to enable this in VFIO so far. I think I
>> can conti
Paolo Bonzini wrote on 2014-08-07:
> Il 07/08/2014 03:31, Zhang, Yang Z ha scritto:
>> Let me give an example to see whether my concern is a real problem:
>> Guest allocates a vector and set it in IOAPIC entry to deliver
>> interrupt. Later it masks the IOAPIC entry(means stop
Paolo Bonzini wrote on 2014-08-06:
> Il 06/08/2014 16:03, Zhang, Yang Z ha scritto:
>> Paolo Bonzini wrote on 2014-07-31:
>>> Probably, the guest is masking the interrupt in the redirection
>>> table in the interrupt routine, i.e. while the interrupt is set in a
>&g
Paolo Bonzini wrote on 2014-07-31:
> Currently, the EOI exit bitmap (used for APICv) does not include
> interrupts that are masked. However, this can cause a bug that manifests
> as an interrupt storm inside the guest. Alex Williamson reported the
> bug and is the one who really debugged this; I
Paolo Bonzini wrote on 2014-08-05:
> Il 05/08/2014 09:56, Zhang, Yang Z ha scritto:
>> Wanpeng Li wrote on 2014-08-04:
>>> This patch fix bug
>>> https://bugzilla.kernel.org/show_bug.cgi?id=61411
>>>
>>> TPR shadow/threshold feature is important to spe
Wanpeng Li wrote on 2014-08-04:
> This patch fix bug https://bugzilla.kernel.org/show_bug.cgi?id=61411
>
> TPR shadow/threshold feature is important to speed up the Windows guest.
> Besides, it is a must feature for certain VMM.
>
> We map virtual APIC page address and TPR threshold from L1 VMCS.
Paolo Bonzini wrote on 2014-08-01:
> Il 01/08/2014 02:57, Zhang, Yang Z ha scritto:
>>> TPR_THRESHOLD will be likely written as zero, but the processor
>>> will never use it anyway. It's just a small optimization because
>>> nested_cpu_has(vmcs12, CPU_BASED_
Paolo Bonzini wrote on 2014-07-31:
> Il 31/07/2014 10:03, Wanpeng Li ha scritto:
>>> One thing:
>>>
+ if (nested_cpu_has(vmcs12, CPU_BASED_TPR_SHADOW))
+ vmcs_write32(TPR_THRESHOLD, vmcs12->tpr_threshold);
>>>
>>> I think you can just do this write unconditionally, since most
Paolo Bonzini wrote on 2014-07-17:
> Il 17/07/2014 06:56, Wanpeng Li ha scritto:
>> && nested_exit_intr_ack_set(vcpu)) {
>> int irq = kvm_cpu_get_interrupt(vcpu);
>> +
>> +if (irq < 0 && kvm_apic_vid_enabled(vcpu->kvm))
>> +irq = kvm_get_apic_in
ress and the L2 can boot up, however, slowly. The original idea of
>> this fix vid injection patch is from "Zhang, Yang Z"
>> .
>>
>> Interrupt which delivered by vid should be injected to L1 by L0 if
>> current is in L1, or should be injected
Wanpeng Li wrote on 2014-07-17:
> WARNING: CPU: 9 PID: 7251 at arch/x86/kvm/vmx.c:8719
> nested_vmx_vmexit+0xa4/0x233 [kvm_intel]() Modules linked in: tun
> nfsv3 nfs_acl auth_rpcgss oid_registry nfsv4 dns_resolver nfs fscache
> lockd sunrpc pci_stub netconsole kvm_intel kvm bridge stp llc autofs4
Paolo Bonzini wrote on 2014-05-26:
> Il 26/05/2014 05:44, Zhang, Yang Z ha scritto:
>> Paolo Bonzini wrote on 2014-05-23:
>>> When Hyper-V enlightenments are in effect, Windows prefers to issue
>>> an Hyper-V MSR write to issue an EOI rather than an x2apic MSR write.
&
Paolo Bonzini wrote on 2014-05-23:
> When Hyper-V enlightenments are in effect, Windows prefers to issue an
> Hyper-V MSR write to issue an EOI rather than an x2apic MSR write.
> The Hyper-V MSR write is not handled by the processor, and besides
> being slower, this also causes bugs with APIC virtu
Konrad Rzeszutek Wilk wrote on 2013-11-09:
> The 'read_reply' works with 'process_msg' to read of a reply in XenBus.
> 'process_msg' is running from within the 'xenbus' thread. Whenever a
> message shows up in XenBus it is put on a xs_state.reply_list list and
> 'read_reply' picks it up.
>
> The p
Alex Williamson wrote on 2013-12-24:
> David,
>
> Any comments on this patch? Thanks,
>
Hi Alex,
There do have some IOMMUs will treat SNP bit in the PTE as reserved (0) and
will cause a reserved field violation fault if it is set but hardware not
support snoop-control(bit 7 in ECAP_REG is 0)
Randy Dunlap wrote on 2013-04-18:
> On 04/17/13 17:35, Zhang, Yang Z wrote:
>> David Rientjes wrote on 2013-04-18:
>>> On Wed, 17 Apr 2013, Randy Dunlap wrote:
>>>
>>>> On 04/17/13 16:12, David Rientjes wrote:
>>>>> The build fails when CON
David Rientjes wrote on 2013-04-18:
> On Wed, 17 Apr 2013, Randy Dunlap wrote:
>
>> On 04/17/13 16:12, David Rientjes wrote:
>>> The build fails when CONFIG_SMP is disabled:
>>>
>>> arch/x86/kvm/vmx.c: In function 'vmx_deliver_posted_interrupt':
>>> arch/x86/kvm/vmx.c:3950:3: error: 'apic
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