for eMMC (due to
8-bit bus width support)? So from a block device perspective we would
have always have mmcblk0 and mmcblk1.
Otherwise it would conflict with U-Boot's current fixup[1], so
U-Boot's DT would either need to deviate or create boot script breakages
there.
Cheers,
Andre
[1]
https://source.denx.de/u-boot/u-boot/-/blob/master/arch/arm/dts/sunxi-u-boot.dtsi#L14-16
t/arm64: mte: common: Fix write() warnings")
> >
> > are missing a Signed-off-by from their author.
>
> Thanks Stephen. Now fixed.
Thanks Catalin, and apologies for the blunder, that's what I get from
trying multitasking with just a single X chromosome ;-)
Cheers,
Andre
DT, where the kernel is the
authority, but it might help to solve this problem?
Or any other way, which involves U-Boot patching the DTB? (This would
apply to the DTB passed to the kernel, regardless of where and when
it's loaded from)
Any opinions?
Cheers,
Andre
> Enter the current patch: I c
c Zyngier
> Link: https://lore.kernel.org/r/20201209060932.212364-6-jianyong...@arm.com
Reviewed-by: Andre Przywara
Cheers,
Andre
> ---
> drivers/clocksource/arm_arch_timer.c | 2 ++
> include/linux/clocksource_ids.h | 1 +
> 2 files changed, 3 insertions(+)
>
> diff
ommon.c.
>
> Signed-off-by: Jianyong Wu
> Signed-off-by: Marc Zyngier
> Link: https://lore.kernel.org/r/20201209060932.212364-4-jianyong...@arm.com
Verified that the code movements are correct. Test compiled for x86.
1.5 nits below, but regardless:
Reviewed-by: Andre Przywara
the
IRQ controller is in a generic .dtsi (as it usually is), but the
interrupt map is only in *some* of the board .dts files.
What is the problem of just putting #address-cells = <0>; in the
IRQ controller node, after checking that there currently no interrupt
maps in use and no IRQ children? A
On Tue, 2 Feb 2021 15:55:50 +0800
Chen-Yu Tsai wrote:
Hi,
> On Thu, Jan 28, 2021 at 1:26 AM Andre Przywara wrote:
> >
> > The AXP305 PMIC used in AXP805 seems to be fully compatible to the
> ^
> This statement doesn't quite make sense. I as
On Sun, 31 Jan 2021 14:44:40 +0100
Jernej Škrabec wrote:
Hi Jernej,
> Dne sreda, 27. januar 2021 ob 18:24:52 CET je Andre Przywara napisal(a):
> > Add the obvious compatible name to the existing RTC binding, and pair
> > it with the existing H6 fallback compatible string, as
On Thu, 28 Jan 2021 11:36:01 +
Mark Brown wrote:
> On Thu, Jan 28, 2021 at 11:11:28AM +0000, Andre Przywara wrote:
> > Dmitry Torokhov wrote:
> > > On Wed, Jan 27, 2021 at 05:24:45PM +, Andre Przywara wrote:
>
> > > > Check for the regmap_
On Wed, 27 Jan 2021 11:42:15 -0800
Dmitry Torokhov wrote:
Hi Dmitry,
thanks for your feedback!
> On Wed, Jan 27, 2021 at 05:24:45PM +0000, Andre Przywara wrote:
> > On at least one board (Orangepi Zero2) the AXP305 PMIC does not have its
> > interrupt line connected to the CPU
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31
Add the obvious compatible name to the existing RTC binding, and pair
it with the existing H6 fallback compatible string, as the devices are
compatible.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++
1 file
Use enums to group all compatible devices together on the way.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Maxime Ripard
Reviewed-by: Guenter Roeck
---
.../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +---
1 file changed, 5 insertions(+), 7 deletions
Add the obvious compatible name to the existing IR binding, and pair
it with the existing A31 fallback compatible string, as the devices
are compatible.
On the way use enums to group all compatible devices together.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/media
Add the obvious compatible name to the existing RSB binding, and pair
it with the existing A23 fallback compatible string, as the devices are
compatible.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/bus/allwinner,sun8i-a23-rsb.yaml | 4 +++-
1 file changed, 3 insertions(+), 1
Add the obvious compatible name to the existing SPI binding, and pair
it with the existing H3 fallback compatible string, as the devices are
compatible.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
1 file
On Wed, 27 Jan 2021 17:15:30 +
Mark Brown wrote:
> On Mon, 25 Jan 2021 15:17:50 +0000, Andre Przywara wrote:
> > an update from the v3 last week, to add support for the Allwinner H616
> > SoC. Still based on the (updated) sunxi/for-next branch.
> > I am omitting the MM
regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers
Add the obvious compatible name to the existing EMAC binding, and pair
it with the existing A64 fallback compatible string, as the devices are
compatible.
On the way use enums to group the compatible devices together.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/net/allwinner
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 08607c7ec1bf..aeb8771b14c4
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre
ls.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++-
interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 573 ++
1 file changed, 573 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616
Add the obvious compatible name to the existing I2C binding, and pair
it with the existing A31 fallback compatible string, as the devices
are compatible.
On the way use enums to group all compatible devices together.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Wolfram Sang
e_register+0x20/0x30
[4.120065] sunxi_rsb_probe+0x4e4/0x608
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/633392.html
Signed-off-by: Andre Przywara
---
drivers/input/misc/axp20x-pek.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/input/m
The H616 adds a second EMAC clock register. We don't know about the
exact SRAM properties yet, so this gets omitted for now.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 +
1 file changed, 1 insertion(+)
rrupt functionality of the AXP chip is simply not available.
Check whether the interrupt line number returned by the platform code is
valid, before trying to register the irqchip. If not, we skip this
registration, to avoid the driver to bail out completely.
Signed-off-by: Andre Przywara
---
driver
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig
The AXP305 PMIC used in AXP805 seems to be fully compatible to the
AXP805 PMIC, so add the proper chain of compatible strings.
Also at least on one board (Orangepi Zero2) there is no interrupt line
connected to the CPU, so make the "interrupts" property optional.
Signed-off-by: Andr
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
t is now merged into its master tree.
Thanks!
Andre
==
This series gathers patches to support the Allwinner H616 SoC. This is
a rather uninspired SoC (Quad-A53 with the usual peripherals), but
allows for some cheap development boards and TV boxes, and supports
up to 4GB of DRAM.
Var
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Maxime Ripard
---
.../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml| 4
1 file changed, 4 insertions(+)
diff --git
a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
b/Documentation
.dts, or even some "common peripherals" intermediate .dts.
Possibly even in an overlay (I2C IRQ lines?).
So while not having this property works today, for your board, it might
surprisingly break for someone else. And those things are hard to find
(unless you know what you are looking for).
interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 ++
1 file changed, 750 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616
assign a new
compatible name to it.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 539209fe3468
On Mon, 25 Jan 2021 23:51:01 +0100
Alexandre Belloni wrote:
Hi Alexandre,
> On 25/01/2021 15:18:02+0000, Andre Przywara wrote:
> > Add the obvious compatible name to the existing RTC binding, and pair
> > it with the existing H6 fallback compatible string, as the devices are
ments).
I eventually got USB to work, by requiring PHY 2 for [EO]HCI 1 & 3 as well.
Not sure this is the right fix, it might be just one clock or reset
line from that PHY that is needed for the others as well. Will do further
experiments.
For a more detailed changelog, see below.
regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers
Add the obvious compatible name to the existing IR binding, and pair
it with the existing A31 fallback compatible string, as the devices
are compatible.
On the way use enums to group all compatible devices together.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/media
Use enums to group all compatible devices together on the way.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Maxime Ripard
Reviewed-by: Guenter Roeck
---
.../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +---
1 file changed, 5 insertions(+), 7 deletions
Add the obvious compatible name to the existing RTC binding, and pair
it with the existing H6 fallback compatible string, as the devices are
compatible.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/rtc/allwinner,sun6i-a31-rtc.yaml | 3 +++
1 file
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 08607c7ec1bf..aeb8771b14c4
The H616 has four PHYs as the H3, along with their respective clock
gates and resets, so the property description is identical.
However the PHYs itself need some special bits, so we need a new
compatible string for it.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/phy/allwinner
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre
Add the obvious compatible name to the existing I2C binding, and pair
it with the existing A31 fallback compatible string, as the devices
are compatible.
On the way use enums to group all compatible devices together.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Wolfram Sang
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
Acked-by: Maxime Ripard
---
.../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
b/Documentation
ls.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++-
The AXP305 PMIC used in AXP805 seems to be fully compatible to the
AXP805 PMIC, so add the proper chain of compatible strings.
Also at least on one board (Orangepi Zero2) there is no interrupt line
connected to the CPU, so make the "interrupts" property optional.
Signed-off-by: Andr
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31
On Sun, 17 Jan 2021 22:28:47 -0600
Samuel Holland wrote:
Hi,
> On 1/17/21 8:08 PM, Andre Przywara wrote:
> > Add simple "allwinner,sun50i-h616-xxx" compatible names to existing
> > bindings, and pair them with an existing fallback compatible string,
> > as the d
Add the obvious compatible name to the existing SPI binding, and pair
it with the existing H3 fallback compatible string, as the devices are
compatible.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/spi/allwinner,sun6i-a31-spi.yaml | 1 +
1 file
rrupt functionality of the AXP chip is simply not available.
Check whether the interrupt line number returned by the platform code is
valid, before trying to register the irqchip. If not, we skip this
registration, to avoid the driver to bail out completely.
Signed-off-by: Andre Przywara
---
driver
The H616 MUSB peripheral is presumably compatible to the H3 one.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/usb/allwinner
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
---
drivers/clk/sunxi-ng/Kconfig
The H616 adds a second EMAC clock register. We don't know about the
exact SRAM properties yet, so this gets omitted for now.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 +
1 file changed, 1 insertion(+)
e_register+0x20/0x30
[4.120065] sunxi_rsb_probe+0x4e4/0x608
[1]
http://lists.infradead.org/pipermail/linux-arm-kernel/2021-January/633392.html
Signed-off-by: Andre Przywara
---
drivers/input/misc/axp20x-pek.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/input/m
On Sun, 17 Jan 2021 21:37:22 -0600
Samuel Holland wrote:
Hi Samuel,
thanks for your input!
> On 1/17/21 8:08 PM, Andre Przywara wrote:
> > Currently the AXP chip requires to have its IRQ line connected to some
> > interrupt controller, and will fail probing when this
On Wed, 20 Jan 2021 13:26:26 +
Marc Zyngier wrote:
Hi,
> On 2021-01-20 13:01, Will Deacon wrote:
> > On Wed, 6 Jan 2021 10:34:48 +0000, Andre Przywara wrote:
> >> a fix to v5, now *really* fixing the wrong priority of SMCCC vs.
> >> RNDR in arch_get_random_seed_
On Mon, 18 Jan 2021 14:28:54 +0100
Maxime Ripard wrote:
Hi Maxime,
> On Mon, Jan 18, 2021 at 02:08:29AM +0000, Andre Przywara wrote:
> > From: Yangtao Li
> >
> > This patch adds support for A100 MMC controller, which use word
> > address for internal dma.
> &g
Use enums to group all compatible devices together on the way.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 12 +---
1 file changed, 5 insertions(+), 7 deletions(-)
diff --git
a/Documentation/devicetree/bindings
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml | 2 ++
1 file changed, 2 insertions(+)
diff --git
a/Documentation/devicetree/bindings/clock/allwinner,sun4i-a10-ccu.yaml
b/Documentation/devicetree/bindings/clock
There are only two pins left now, used to connect to the PMIC via I2C.
Signed-off-by: Andre Przywara
Acked-by: Maxime Ripard
Reviewed-by: Jernej Skrabec
---
drivers/pinctrl/sunxi/Kconfig | 5 ++
drivers/pinctrl/sunxi/Makefile| 1 +
drivers/pinctrl/sunxi
The clocks itself are identical to the H6 R-CCU, it's just that the H616
has not all of them implemented (or connected).
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig | 2 +-
drivers/clk/sunxi-ng/ccu-sun50i-h6-r.c | 48 ++
2 files change
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml
b/Documentation/devicetree/bindings/arm/sunxi.yaml
index 7ea4d9645e93..6a2fa84bb785
The Allwinner H616 adds a second EMAC clock register at offset 0x34, for
controlling the second EMAC in this chip.
Allow to extend the regmap in this case, to cover more than the current
4 bytes exported.
Signed-off-by: Andre Przywara
---
drivers/soc/sunxi/sunxi_sram.c | 31
assign a new
compatible name to it.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c
b/drivers/phy/allwinner/phy-sun4i-usb.c
index 539209fe3468..e71d6b8ccf16 100644
--- a
Add simple "allwinner,sun50i-h616-xxx" compatible names to existing
bindings, and pair them with an existing fallback compatible string,
as the devices are compatible.
This covers I2C, infrared, RTC and SPI.
Use enums to group all compatible devices together.
Signed-off-by: Andre Przyw
The H616 MUSB peripheral is presumably compatible to the H3 one.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml | 3 +++
1 file changed, 3 insertions(+)
diff --git
a/Documentation/devicetree/bindings/usb/allwinner,sun4i-a10-musb.yaml
b
The OrangePi Zero 2 is a development board with the new H616 SoC.
It features the usual connectors used on those small boards, and comes
with the AXP305, which seems to be compatible with the AXP805.
For more details see: http://linux-sunxi.org/Xunlong_Orange_Pi_Zero2
Signed-off-by: Andre
interrupt controller anymore, also
it lacks the corresponding NMI pin, so no interrupts for the PMIC.
Signed-off-by: Andre Przywara
---
.../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 750 ++
1 file changed, 750 insertions(+)
create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h616
ls.
While we are at it, generalise the existing code by allowing a bitmap
of bits to clear, to cover newer SoCs: The A100 and H616 use a different
bit for the SIDDQ control.
Signed-off-by: Andre Przywara
---
drivers/phy/allwinner/phy-sun4i-usb.c | 29 +++
1 file chan
The H616 has four PHYs as the H3, along with their respective clock
gates and resets, so the property description is identical.
However the PHYs itself need some special bits, so we need a new
compatible string for it.
Signed-off-by: Andre Przywara
---
.../devicetree/bindings/phy/allwinner
regmap, so that we can address more than the first register, if
needed.
Signed-off-by: Andre Przywara
---
drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c | 12 ++--
1 file changed, 10 insertions(+), 2 deletions(-)
diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-sun8i.c
b/drivers
describes the AXP chip as an interrupt controller
before trying to register the irqchip, to avoid probe failures on
setups without an interrupt.
Signed-off-by: Andre Przywara
---
drivers/mfd/axp20x.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/drivers/mfd
While the clocks are fairly similar to the H6, many differ in tiny
details, so a separate clock driver seems indicated.
Derived from the H6 clock driver, and adjusted according to the manual.
Signed-off-by: Andre Przywara
---
drivers/clk/sunxi-ng/Kconfig|5 +
drivers/clk
The H616 adds a second EMAC clock register. We don't know about the
exact SRAM properties yet, so this gets omitted for now.
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../bindings/sram/allwinner,sun4i-a10-system-control.yaml| 1 +
1 file changed, 1 insertion(+)
Port A is used for an internal connection to some analogue circuitry
which looks like an AC200 IP (as in the H6), though this is not
mentioned in the manual.
Signed-off-by: Andre Przywara
---
drivers/pinctrl/sunxi/Kconfig | 5 +
drivers/pinctrl/sunxi/Makefile | 1
A new SoC, a new compatible string.
Also we were too miserly with just allowing seven interrupt banks.
Signed-off-by: Andre Przywara
---
.../pinctrl/allwinner,sun4i-a10-pinctrl.yaml| 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git
a/Documentation
From: Yangtao Li
This patch adds support for A100 MMC controller, which use word address
for internal dma.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
---
drivers/mmc/host/sunxi-mmc.c | 28 +---
1 file changed, 25 insertions(+), 3 deletions(-)
diff --git
From: Yangtao Li
Add binding for A100's and H616's mmc and emmc controller.
Signed-off-by: Yangtao Li
Signed-off-by: Andre Przywara
Acked-by: Rob Herring
---
.../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 8
1 file changed, 8 insertions(+)
diff --git a/Doc
gets
fixed in U-Boot, we can remove this from the .dtsi.
For a more detailed changelog, see below.
Thanks!
Andre
==
This series gathers patches to support the Allwinner H616 SoC. This is
a rather uninspired SoC (Quad-A53 with the usual peripherals), but
allows for some cheap dev
at bits [4:2] are indeed masked off, so the manual is right.
Change to number of bits in the affected clock's description.
Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
Signed-off-by: Andre Przywara
Reviewed-by: Jernej Skrabec
---
Splitting this
On Mon, 14 Dec 2020 10:37:28 +0100
Maxime Ripard wrote:
> On Fri, Dec 11, 2020 at 01:19:15AM +0000, Andre Przywara wrote:
> > A new SoC, a new compatible string.
> > Also we were too miserly with just allowing seven interrupt banks.
> >
> > Si
function, which returns -1 if this interface is
not implemented.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/archrandom.h | 72 -
1 file changed, 61 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/arch
the kernel's entropy pool only, to avoid guests
draining more precious direct entropy sources.
Signed-off-by: Ard Biesheuvel
[Andre: minor fixes, drop arch_get_random() usage]
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/kvm_host.h | 2 +
arch/arm64/kvm/Makefile
when reseeding.
Cc: Linus Walleij
Cc: Russell King
Signed-off-by: Ard Biesheuvel
[Andre: rework to be initialised by the SMCCC firmware driver]
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
---
arch/arm/Kconfig | 4 ++
arch/arm/include/asm/archrandom.h
of this interface.
For now this return false, but this will be overwritten by each
architecture's support patch.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
arch/arm/include/asm/archrandom.h | 10 ++
arch/arm64/include/asm/archrandom.h
-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
include/linux/arm-smccc.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index f860645f6512..62c54234576c 100644
--- a
common definitions, and is a prerequisite
for every other patch, although they are somewhat independent and likely
will need to go through different subsystems.
Cheers,
Andre
==
The ARM architected TRNG firmware interface, described in ARM spec
DEN0098[1], defines an
On Tue, 5 Jan 2021 17:00:14 +
Mark Brown wrote:
> On Tue, Jan 05, 2021 at 04:36:51PM +0000, Andre Przywara wrote:
>
> > @@ -77,10 +117,20 @@ arch_get_random_seed_long_early(unsigned long
> > *v) {
> > WARN_ON(system_state != SYSTEM_BOOTING);
> >
>
the kernel's entropy pool only, to avoid guests
draining more precious direct entropy sources.
Signed-off-by: Ard Biesheuvel
[Andre: minor fixes, drop arch_get_random() usage]
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/kvm_host.h | 2 +
arch/arm64/kvm/Makefile
function, which returns -1 if this interface is
not implemented.
Signed-off-by: Andre Przywara
---
arch/arm64/include/asm/archrandom.h | 72 -
1 file changed, 61 insertions(+), 11 deletions(-)
diff --git a/arch/arm64/include/asm/archrandom.h
b/arch/arm64/include/asm/arch
when reseeding.
Cc: Linus Walleij
Cc: Russell King
Signed-off-by: Ard Biesheuvel
[Andre: rework to be initialised by the SMCCC firmware driver]
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
---
arch/arm/Kconfig | 4 ++
arch/arm/include/asm/archrandom.h
of this interface.
For now this return false, but this will be overwritten by each
architecture's support patch.
Signed-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
arch/arm/include/asm/archrandom.h | 10 ++
arch/arm64/include/asm/archrandom.h
-off-by: Andre Przywara
Reviewed-by: Linus Walleij
Reviewed-by: Sudeep Holla
---
include/linux/arm-smccc.h | 31 +++
1 file changed, 31 insertions(+)
diff --git a/include/linux/arm-smccc.h b/include/linux/arm-smccc.h
index f860645f6512..62c54234576c 100644
--- a
contains the common definitions, and is a prerequisite
for every other patch, although they are somewhat independent and likely
will need to go through different subsystems.
Cheers,
Andre
==
The ARM architected TRNG firmware interface, described in ARM spec
DEN0098[1
On 05.01.2021 07:54, Greg Kroah-Hartman wrote:
On Mon, Jan 04, 2021 at 08:04:08PM +0100, Andre Tomt wrote:
On 28.12.2020 13:50, Greg Kroah-Hartman wrote:
From: Stylon Wang
commit a135a1b4c4db1f3b8cbed9676a40ede39feb3362 upstream.
EDID parsing in S3 resume pushes new display modes
to
On 28.12.2020 13:50, Greg Kroah-Hartman wrote:
From: Stylon Wang
commit a135a1b4c4db1f3b8cbed9676a40ede39feb3362 upstream.
EDID parsing in S3 resume pushes new display modes
to probed_modes list but doesn't consolidate to actual
mode list. This creates a race condition when
amdgpu_dm_connector
On Fri, 11 Dec 2020 16:26:12 +
Mark Brown wrote:
> On Fri, Dec 11, 2020 at 04:00:04PM +0000, Andre Przywara wrote:
>
> > static inline bool __must_check arch_get_random_seed_long(unsigned
> > long *v) {
> > + struct arm_smccc_res res;
> > +
> > + /*
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