From: Ben Peled
When a PCI link down condition is detected, the link training state
machine must be disabled immediately.
Signed-off-by: Marc St-Amand
Signed-off-by: Konstantin Porotchkin
Signed-off-by: Ben Peled
---
drivers/pci/controller/dwc/pcie-armada8k.c | 38
1 fil
From: Ben Peled
Adding optional system-controller and mac-reset-bit-mask
needed for linkdown procedure.
Signed-off-by: Ben Peled
---
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-armada
From: Ben Peled
Add system controller and reset bit to each pcie to enable pcie mac reset
Signed-off-by: Ben Peled
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/m
From: Ben Peled
Added pcie reset via gpio support as described in the
designware-pcie.txt DT binding document.
In cases link down cause still exist in device.
The device need to be reset to reestablish the link.
If reset-gpio pin provided in the device tree, then the linkdown
handle resets the de
From: Ben Peled
The following patches implement the required procedure to handle and recover
from asynchronous PCIE link down events on Armada SoCs.
The procedure is defined as the following:
1) Prevent new access to the PCI-E I/F by disabling the LTSSM
2) Flush all pending transaction/access t
From: Ben Peled
In PCIE ISR routine caused by RST_LINK_DOWN
we schedule work to handle the link-down procedure.
Link-down procedure will:
1. Remove PCIe bus
2. Reset the MAC
3. Reconfigure link back up
4. Rescan PCIe bus
Signed-off-by: Ben Peled
---
drivers/pci/controller/dwc/pcie-armada8k.c |
From: Ben Peled
When a PCI link down condition is detected, the link training state
machine must be disabled immediately.
Signed-off-by: Marc St-Amand
Signed-off-by: Konstantin Porotchkin
Signed-off-by: Ben Peled
---
drivers/pci/controller/dwc/pcie-armada8k.c | 38
1 fil
From: Ben Peled
The following patches implement the required procedure to handle and recover
from asynchronous PCIE link down events on Armada SoCs.
The procedure is defined as the following:
1) Prevent new access to the PCI-E I/F by disabling the LTSSM
2) Flush all pending transaction/access t
From: Ben Peled
In PCIE ISR routine caused by RST_LINK_DOWN
we schedule work to handle the link-down procedure.
Link-down procedure will:
1. Remove PCIe bus
2. Reset the MAC
3. Reconfigure link back up
4. Rescan PCIe bus
Signed-off-by: Ben Peled
---
drivers/pci/controller/dwc/pcie-armada8k.c |
From: Ben Peled
Added pcie reset via gpio support as described in the
designware-pcie.txt DT binding document.
In cases link down cause still exist in device.
The device need to be reset to reestablish the link.
If reset-gpio pin provided in the device tree, then the linkdown
handle resets the de
From: Ben Peled
Add system controller and reset bit to each pcie to enable pcie mac reset
Signed-off-by: Ben Peled
---
arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi
b/arch/arm64/boot/dts/m
From: Ben Peled
Adding optional system-controller and mac-reset-bit-mask
needed for linkdown procedure.
Signed-off-by: Ben Peled
---
Documentation/devicetree/bindings/pci/pci-armada8k.txt | 6 ++
1 file changed, 6 insertions(+)
diff --git a/Documentation/devicetree/bindings/pci/pci-armada
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