magic numbers, and could not be revealed. These magic numbers are
received from Realtek via Pine64.
Signed-off-by: Icenowy Zheng
---
drivers/net/phy/realtek.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/drivers/net/phy/realtek.c b/drivers/net/phy/realtek.c
index 677c45985338
Some of the Pine64+ boards are known to use a batch of broken RTL8211E
PHYs. A magic number that is in an undocumented field of a register is
passed from Realtek via Pine64.
Add the property to apply the hack to the Pine64+ device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts
From: Icenowy Zheng
Some RTL8211E Ethernet PHY have an issue that needs a workaround, and a
way to indicate the need of the workaround should be added.
Add the binding for a DT property that indicates this workaround.
Signed-off-by: Icenowy Zheng
---
.../bindings/net/realtek,rtl8211e.yaml
There're some Pine64+ boards known to have broken RTL8211E chips, and
a hack is given by Pine64+, which is said to be from Realtek.
This patchset adds the hack.
The hack is taken from U-Boot, and it contains magic numbers without
any document.
Icenowy Zheng (3):
dt-bindings: add bindin
在 2019-08-20二的 15:58 +0200，Maxime Ripard写道：
> On Fri, Aug 16, 2019 at 04:00:16PM +0200, Corentin Labbe wrote:
> > On Fri, Aug 16, 2019 at 03:52:06PM +0200, Maxime Ripard wrote:
> > > On Fri, Aug 16, 2019 at 01:57:50PM +0200, Corentin Labbe wrote:
> > > > On Fri, Aug 16, 2019 at 01:36:50PM +0200, Ma
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Added missing compatible string.
- Set default USB role to "peripheral".
- Switch to use V3 DTSI.
No changes in v4.
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3
t of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix MMC2 clock slices.
Changes in v4:
- Add the missing MMC2 clock slices.
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +-
drivers/clk/sunxi-ng/
the file's name.
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Dropped dedicated S3/S3L DTSIs.
No changes until v5.
arch/arm/boot/dts/sun8i-v3.dtsi | 14 ++
1 file changed, 14 insertions(+)
create mode 100644 arch/arm/boot/dts/sun8i-v3.dtsi
diff --git a/arch/arm/boot/dts/
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
Changes in v5:
- Fix typo on hw_clk reference.
Patch introduced in v4.
d
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
---
No changes in v5.
Changes in v4:
- Removed bogus alignment change.
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
---
Changes in v5:
- Added V3 compatible to S3 board.
- Fixed S3 compatible string.
No changes until v5
s the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (6):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
clk: sunxi-ng
在 2019-07-23 03:29，Maxime Ripard 写道：
On Sat, Jul 20, 2019 at 07:39:08PM +0800, Icenowy Zheng wrote:
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard
写到:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a
于 2019年7月20日 GMT+08:00 下午6:13:18, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:33AM +0800, Icenowy Zheng wrote:
>> The Lichee Zero Plus is a core board made by Sipeed, with a microUSB
>> connector on it, TF slot or WSON8 SD chip, optional eMMC or SPI
>Flash.
>&
于 2019年7月20日 GMT+08:00 下午5:48:14, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:32AM +0800, Icenowy Zheng wrote:
>> The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
>> but with more GPIO wired out of the package.
>>
>> Add DTSI files for these
于 2019年7月20日 GMT+08:00 下午5:44:49, Maxime Ripard 写到:
>On Sat, Jul 13, 2019 at 11:46:30AM +0800, Icenowy Zheng wrote:
>> The MMC2 clock slices are currently not defined in V3s CCU driver,
>which
>> makes MMC2 not working.
>>
>> Fix this issue.
>>
>>
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes since v3.
Patch introduced in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes in v4.
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3 regulator.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
but with more GPIO wired out of the package.
Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
pinctrl compatible string, and the S3/S3L DTSI files just include the V3
DTSI file.
Signed-off-by: Icenowy
t of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Add the missing MMC2 clock slices.
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 228 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindi
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes since v1.
drivers/clk/sunxi-ng/
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.
Fix this issue.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 3 +++
1 file
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Removed bogus alignment change.
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number.
Changes in v2:
- Dropped the driver rename patch
s the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (8):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add the missing PLL_DDR1
dt-bindings: clk: sunxi-ccu: add compa
于 2019年6月24日 GMT+08:00 下午8:43:01, Maxime Ripard 写到:
>On Sun, Jun 23, 2019 at 12:38:01PM +0800, Icenowy Zheng wrote:
>> Lichee zero plus is a core board made by Sipeed, which includes
>on-board
>> TF slot or SMT SD NAND, and optional SPI NOR or eMMC, a UART debug
>> hea
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Drop common regulator DTSI usage and added vcc3v3 regulator.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
.../dts/sun8i-s3-s3l
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
but with more GPIO wired out of the package.
Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
pinctrl compatible string, and the S3/S3L DTSI files just include the V3
DTSI file.
Signed-off-by: Icenowy
Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
EVBs with Allwinner chips. There's also a SoC named S3 that is developed
by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
Add the vendor prefix for SoChip.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob He
t of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
No changes in v3/v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 225 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindi
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
No changes in v3.
Patch introduced in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5
Shenzhen Sipeed Technology Co., Ltd. is a company focused on development
kits, which also contains rebranded Lichee Pi series.
Add its vendor prefix binding.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Rebased because of the addition of sinlinx and sinovoip.
Patch introduced in v2
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v3:
- Fixed code alignment.
- Fixed LVDS function number.
Changes in v2:
- Dropped the driver rename patch and apply the changes directly on V3s
driver
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes in v3/v2.
drivers/clk/sunxi-ng/
s the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (9):
pinctrl: sunxi: v3s: introduce support for V3
clk: sunxi-ng: v3s: add the missing PLL_DDR1
dt-bindings: clk: sunxi-ccu: add compa
Shenzhen SoChip Technology Co., Ltd. is a hardware vendor that produces
EVBs with Allwinner chips. There's also a SoC named S3 that is developed
by Allwinner (based on Allwinner V3/V3s) but branded SoChip.
Add the vendor prefix for SoChip.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob He
SoCs.
Add the device tree binding of the basic version of the core board --
w/o eMMC or SPI Flash, w/ TF slot or WSON8 SD, and use S3 SoC.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +
1 file changed, 5 insertions(+)
diff --git a
Shenzhen Sipeed Technology Co., Ltd. is a company focused on development
kits, which also contains rebranded Lichee Pi series.
Add its vendor prefix binding.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++
1 file changed, 2
The Allwinner S3/S3L/V3 SoCs all share the same die with the V3s SoC,
but with more GPIO wired out of the package.
Add DTSI files for these SoCs. The DTSI file for V3 just replaces the
pinctrl compatible string, and the S3/S3L DTSI files just include the V3
DTSI file.
Signed-off-by: Icenowy
Introduce the GPIO pins that is only available on V3 (not on V3s) to the
V3s pinctrl driver.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped the driver rename patch and apply the changes directly on V3s
driver.
drivers/pinctrl/sunxi/pinctrl-sun8i-v3s.c | 265
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.
Add back the missing PLL_DDR1.
Fixes: d0f11d14b0bc ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng
---
No changes in v2.
drivers/clk/sunxi-ng/ccu-s
The Allwinner V3 SoC, despite come with the same die with V3s, has more
GPIO pins than V3s, and a different compatible string for pinctrl is
needed.
Add the compatible string for V3 pinctrl.
Signed-off-by: Icenowy Zheng
Reviewed-by: Rob Herring
---
Changes in v2:
- Add the review tag by Rob
board, w/o optional onboard
storage, and with S3 SoC.
Signed-off-by: Icenowy Zheng
---
New patch in v2.
arch/arm/boot/dts/Makefile| 1 +
.../boot/dts/sun8i-s3-lichee-zero-plus.dts| 8
.../dts/sun8i-s3-s3l-lichee-zero-plus.dtsi| 39 +++
3 files
Despite Allwinner V3 and V3s shares the same die, one peripheral (I2S)
is only available on V3, and thus the clocks is not declared for V3s
CCU.
Add a V3 CCU compatible string to the binding to prepare for a CCU
driver that provide I2S clock on V3, but not on V3s.
Signed-off-by: Icenowy Zheng
t of the device tree binding (the header file name).
Signed-off-by: Icenowy Zheng
---
No changes in v2.
drivers/clk/sunxi-ng/ccu-sun8i-v3s.c | 225 +-
drivers/clk/sunxi-ng/ccu-sun8i-v3s.h | 2 +-
include/dt-bindings/clock/sun8i-v3s-ccu.h | 4 +
include/dt-bindings/
The pinctrl driver of V3s is already available and used in the kernel,
but the compatible string of it is forgotten to be added.
Add the missing compatible string.
Signed-off-by: Icenowy Zheng
Acked-by: Maxime Ripard
Reviewed-by: Rob Herring
---
Changes in v2:
- Add the ACK tag by Maxime and
s the features missing on V3s for using them on
V3/S3/S3L, and add bindings for V3/S3/S3L. It also adds a S3 SoM by
Sipeed, called Lichee Zero Plus.
Icenowy Zheng (11):
dt-bindings: pinctrl: add missing compatible string for V3s
dt-bindings: pinctrl: add compatible string for Allwinner V3 pi
在 2019-05-06一的 14:28 +0200，Maxime Ripard写道：
> Hi,
>
> On Sun, May 05, 2019 at 04:22:15PM +0100, Jonathan Cameron wrote:
> > On Fri, 3 May 2019 03:28:07 -0400
> > Yangtao Li wrote:
> >
> > > For some SOCs, there are more than one thermal sensor, and there
> > > are
> > > currently four sensors o
The Allwinner H6 SoC features tweakable VCC for PC, PD, PG, PL and PM
banks.
This patch adds supplies for these banks except PL bank. PL bank is
where PMIC is attached, and currently if a PMIC regulator is added
for it a dependency loop will happen.
Signed-off-by: Icenowy Zheng
---
Changes in
The Allwinner V3/V3s/S3L/SoChip S3 Ethernet MAC and internal PHY is quite
similar to the ones on Allwinner H3, except for V3s the external MII is
not wired out.
Add ethernet support to V3/V3s/S3/S3L.
Signed-off-by: Icenowy Zheng
---
arch/arm/boot/dts/sun8i-v3.dtsi | 13
arch/arm/boot
initialization code is not
shared because the acquisition of GPIO configuration in OTP ROM is
similar to CP2105, not CP2102N.
Signed-off-by: Icenowy Zheng
---
drivers/usb/serial/cp210x.c | 82 +++--
1 file changed, 78 insertions(+), 4 deletions(-)
diff --git a/drivers/usb
The SMI SM3350 USB-UFS bridge controller cannot handle long sense request
correctly and will make the chip refuse to do read/write when requested
long sense.
Add a bad sense quirk for it.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/unusual_devs.h | 12
1 file changed, 12
US_FL_BAD_SENSE for SM3350 fail
(as it claims SPC4).
Fix this conflicting quirk issue, and add the quirk for SM3350.
Icenowy Zheng (2):
USB: storage: don't insert sane sense for SPC3+ when bad sense
specified
USB: storage: add quirk for SMI SM3350
drivers/usb/storage/scsiglue.c
state that cannot read/write anything).
Check the presence of US_FL_BAD_SENSE when assuming US_FL_SANE_SENSE on
SPC4+ devices.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Changed the comment to note the check.
drivers/usb/storage/scsiglue.c | 8 ++--
1 file changed, 6 insertions
在 2018-12-27四的 22:34 +0800，Icenowy Zheng写道：
> The SMI SM3350 USB-UFS bridge controller cannot handle long sense
> request
> correctly and will make the chip refuse to do read/write when
> requested
> long sense.
>
> Add a bad sense quirk for it.
>
> Signed-off-by: Ice
在 2018-12-27四的 22:34 +0800，Icenowy Zheng写道：
> Currently the code will set US_FL_SANE_SENSE flag unconditionally if
> device claims SPC3+, however we should allow US_FL_BAD_SENSE flag to
> prevent this behavior, because SMI SM3350 UFS-USB bridge controller,
> which claims SPC4, will
state that cannot read/write anything).
Check the presence of US_FL_BAD_SENSE when assuming US_FL_SANE_SENSE on
SPC4+ devices.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/scsiglue.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/storage/scsiglue.c b
The SMI SM3350 USB-UFS bridge controller cannot handle long sense request
correctly and will make the chip refuse to do read/write when requested
long sense.
Add a bad sense quirk for it.
Signed-off-by: Icenowy Zheng
---
drivers/usb/storage/unusual_devs.h | 12
1 file changed, 12
US_FL_BAD_SENSE for SM3350 fail
(as it claims SPC4).
Fix this conflicting quirk issue, and add the quirk for SM3350.
Icenowy Zheng (2):
USB: storage: don't insert sane sense for SPC3+ when bad sense
specified
USB: storage: add quirk for SMI SM3350
drivers/usb/storage/scsiglue.c
nodes")
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
index 45bbb5116446..d1ed451f4d9e 100644
于 2018年11月13日 GMT+08:00 下午1:50:45, Sasha Levin 写到:
>From: Icenowy Zheng
>
>[ Upstream commit c2ff8383cc33c2d9c169e4daf1e37a434c3bb420 ]
>
>On the H6, the MMC module clocks are fixed in the new timing mode,
>i.e. they do not have a bit to select the mode. These clocks
From: Jagan Teki
The HDMI controller on Allwinner A64 is similar on the one on
H3/H5/A83T (although the PHY is different with A83T).
Add A64 compatible and append A83T compatible as fallback.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy: refactor commit log]
Signed-off-by
From: Jernej Skrabec
Some boards have HDMI VCC pin connected to voltage regulator which may
not be turned on by default.
Add support for such boards by adding voltage regulator handling code to
HDMI driver.
Signed-off-by: Jernej Skrabec
[Icenowy: change supply name to "hvcc"]
Sig
From: Jagan Teki
Enable all necessary device tree nodes and add connector node to device
trees for all supported A64 boards with HDMI.
Signed-off-by: Jagan Teki
[Icenowy: squash all board patches altogether and change supply name]
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rebase some
Allwiner SoCs with DesignWare HDMI controller all come with a "HVCC"
pin, which is the VCC of HDMI part.
Add a supply property to specify HVCC's regulator in the device tree.
Signed-off-by: Icenowy Zheng
---
Changes in v4:
- Rename the supply name to "hvcc".
Cha
From: Jagan Teki
Allwinner A64 HDMI PHY clock has PLL_VIDEO0 as a parent.
Include the macro on dt-bindings so-that the same can be used
while defining CCU clock phandles.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Dropped PLL_VIDEO1
TCON1 HDMI one.
Signed-off-by: Jagan Teki
[Icenowy: refactor commit message and add 1st pipeline]
Signed-off-by: Icenowy Zheng
---
Changes for v4:
- Misc fixes
- Dropped second PLL from HDMI PHY clock
Changes for v3.1:
- Refactor commit message to make it more clear.
- Added first pipeline
From: Jagan Teki
Display Engine(DE2) in Allwinner A64 has two mixers and tcons.
The routing for mixer0 is through tcon0 and connected to
LVDS/RGB/MIPI-DSI controller.
The routing for mixer1 is through tcon1 and connected to HDMI.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy Zheng
From: Jagan Teki
Mixers in Allwinner have similar capabilities as others SoCs with DE2.
Add support for them.
Signed-off-by: Jagan Teki
[Icenowy: Add mixer1]
Signed-off-by: Icenowy Zheng
Reviewed-by: Jernej Skrabec
---
Changes for v4:
- none
Changes for v3.1:
- Add mixer0
Changes for v3
From: Jagan Teki
According to documentation and experience with other similar SoCs, video
PLLs don't work stable if their output frequency is set below 192 MHz.
Because of that, set minimal rate to both A64 video PLLs to 192 MHz.
Signed-off-by: Jagan Teki
Signed-off-by: Icenowy
From: Jagan Teki
Allwinner A64 has a DE2 display pipeline. The TCONs are similar to the
ones in A83T, but the mixers are new (similar to the later R40 SoC).
This patch adds dt-binding documentation for A64 DE2 display pipeline.
Signed-off-by: Jagan Teki
Reviewed-by: Rob Herring
[Icenowy
other SoCs, so more faith is put in BSP clock driver.
Signed-off-by: Icenowy Zheng
---
New patch in v4.
drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 50 ++-
1 file changed, 26 insertions(+), 24 deletions(-)
diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c
b/drivers/clk
r the two display pipelines, and enables
the HDMI output on several boards. The first pipeline is not enabled in
this patchset yet, although it's added.
Icenowy Zheng (2):
clk: sunxi-ng: a64: Add max. rate constraint to video PLLs
dt-bindings: sun4i-drm: add HDMI VCC supply property fo
在 2017-09-26二的 09:22 +0200，Corentin Labbe写道：
> The unit address and register address does not match.
> This patch fix the register address with the good one.
>
> Acked-by: Maxime Ripard
> Signed-off-by: Corentin Labbe
This patch should be backported.
Older LTS also needs patches, but the patch
于 2018年7月25日 GMT+08:00 下午11:31:26, Rob Herring 写到:
>On Sun, Jul 22, 2018 at 02:10:33PM +0800, Chen-Yu Tsai wrote:
>> On Sun, Jul 22, 2018 at 1:57 PM, Icenowy Zheng
>wrote:
>> > The new Allwinner H6 SoC contains a USB3 PHY that is wired to the
>> > external USB3
于 2018年7月25日 GMT+08:00 下午8:19:47, Maxime Ripard 写到:
>On Tue, Jul 24, 2018 at 10:42:32PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月24日 GMT+08:00 下午10:41:51, Maxime Ripard
> 写到:
>> >On Tue, Jul 24, 2018 at 10:37:51AM +0800, Chen-Yu Tsai wrote:
>&
e-run dw_hdmi_setup when setting mode, in order to prevent such
situation.
Signed-off-by: Icenowy Zheng
---
drivers/gpu/drm/bridge/synopsys/dw-hdmi.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
b/drivers/gpu/drm/bridge/synopsys/dw-hdmi.c
于 2018年7月12日 GMT+08:00 下午2:46:01, Maxime Ripard 写到:
>On Wed, Jul 11, 2018 at 11:15:50PM +0800, Icenowy Zheng wrote:
>>
>>
>> 于 2018年7月11日 GMT+08:00 下午11:05:32, Maxime Ripard
> 写到:
>> >Hi,
>> >
>> >On Wed, Jul 11, 2018 at 09:22:32PM +0800,
在 2018-07-09一的 10:01 +0530，'Kishon Vijay Abraham I' via linux-sunxi写道：
> Hi,
>
> On Friday 06 July 2018 09:08 PM, Icenowy Zheng wrote:
> > Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
> > controlled).
> >
> > Add a driver for i
As the U-Boot bootloader now is also capable of initialize the HDMI on
A64 boards, add a simplefb device tree node for accessing the HDMI
framebuffer initialized by the bootloader.
Signed-off-by: Icenowy Zheng
---
Changes in v2:
- Dropped LCD SimpleFB as it's already added. LCD SimpleFB
Pine H64 board have a USB3 port, which is connected to the USB3 pins of
the H6 SoC, and the 5V power supply is controlled via GPIO (shared with
the power USB ports).
Enable this port.
Signed-off-by: Icenowy Zheng
---
.../boot/dts/allwinner/sun50i-h6-pine-h64.dts | 23 +++
1
Allwinner H6 SoC features USB3 functionality, with a DWC3 controller and
a custom PHY.
Add device tree nodes for them.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 38
1 file changed, 38 insertions(+)
diff --git a/arch/arm64/boot/dts
Add compatible string to use this generic glue layer to support
Allwinner H6 platform's dwc3 controller.
Signed-off-by: Icenowy Zheng
---
drivers/usb/dwc3/dwc3-of-simple.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/usb/dwc3/dwc3-of-simple.c
b/drivers/usb/dwc3/dwc3-of-sim
The Allwinner H6 SoC uses DWC3 controller for USB3.
Add its device tree binding document.
Signed-off-by: Icenowy Zheng
---
.../bindings/usb/allwinner,dwc3.txt | 39 +++
1 file changed, 39 insertions(+)
create mode 100644 Documentation/devicetree/bindings/usb
Allwinner H6 SoC contains a USB3 PHY (with USB2 DP/DM lines also
controlled).
Add a driver for it.
The register operations in this driver is mainly extracted from the BSP
USB3 driver.
Signed-off-by: Icenowy Zheng
---
.../bindings/phy/sun50i-usb3-phy.txt | 24 +++
drivers/phy
This patchset contains USB3 support for Allwinner H6 SoC (DWC3 with a custom
PHY).
The first patch adds the PHY driver, and the second/third patch adds
compatible to adapt DWC3 platform glue to Allwinner platform. The last
two patches are DT changes.
Icenowy Zheng (5):
phy: allwinner: add phy
From: Ondrej Jirman
Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on
Orange Pi PC, then set the power supply of the ARM cores to this
regulator, in order to enable DVFS.
Signed-off-by: Ondrej Jirman
[Icenowy: Enable DVFS in this patch, slight changes and change commit
message
From: Ondrej Jirman
SY8106A is an I2C attached single output regulator made by Silergy Corp,
which is used on several Allwinner H3/H5 SBCs to control the power
supply of the ARM cores.
Add a driver for it.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message, remove enable/disable
From: Ondrej Jirman
SY8106A is an I2C-controlled adjustable voltage regulator made by
Silergy Corp.
Add its device tree binding.
Signed-off-by: Ondrej Jirman
[Icenowy: Change commit message and slight fixes]
Signed-off-by: Icenowy Zheng
Reviewed-by: Chen-Yu Tsai
Acked-by: Rob Herring
This patchset adds dt-bindings and driver for Silergy SY8106A, and then
utilize it on the Orange Pi PC board, which uses SY8016A as its CPUX
(main ARM CPU cluster in an Allwinner SoC) power supply.
The driver's functionality is restricted now, mainly {en,dis}able function
is not yet implemented, a
Allwinner H6 SoC has a R_I2C controller wired to the PL0/PL1 pins, which
are used in the reference design to connect AXP805 PMIC.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20
1 file changed, 20 insertions(+)
diff
Pine H64 board has a PCF8563 dedicated RTC connected to its R_I2C bus.
Enable the R_I2C bus and add the RTC to the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6-pine-h64.dts | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot
Allwinner H6 SoC has also a R_INTC interrupt controller like Allwinner
A64 SoC, but has its base address changed due to the memory map change
in H6.
Add it into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 9 +
1 file changed, 9
Allwinner H6 SoC has a R_PIO pin controller which controls PL and PM
GPIO banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b
Allwinner H6 SoC has a R_PIO pin controller like other Allwinner SoCs,
which controls the PL and PM pin banks.
Add support for it.
Signed-off-by: Icenowy Zheng
---
.../bindings/pinctrl/allwinner,sunxi-pinctrl.txt | 1 +
drivers/pinctrl/sunxi/Kconfig | 4 +
drivers
Allwinner H6 has also a PRCM CCU.
Add its device node into the device tree.
Signed-off-by: Icenowy Zheng
---
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
b/arch/arm64/boot/dts
M CCU driver is introduced. As the
PRCM clock part is totally different with older SoCs (from A31 to H5),
the driver for H6 is a new one, not reusing the old code.
Icenowy Zheng (7):
clk: sunxi-ng: add support for H6 PRCM CCU
arm64: allwinner: h6: add PRCM CCU device node
pinctrl: sunxi: add
e code. If
reliable information is provided furtherly, the driver needs to be
rechecked.
Signed-off-by: Icenowy Zheng
---
.../devicetree/bindings/clock/sunxi-ccu.txt| 3 +-
drivers/clk/sunxi-ng/Kconfig | 5 +
drivers/clk/sunxi-ng/Makefile
于 2018年5月2日 GMT+08:00 下午7:50:19, Jagan Teki 写到:
>On Wed, May 2, 2018 at 5:04 PM, Icenowy Zheng wrote:
>>
>>
>> 于 2018年5月2日 GMT+08:00 下午7:32:50, Maxime Ripard
> 写到:
>>>On Mon, Apr 30, 2018 at 05:10:39PM +0530, Jagan Teki wrote:
>>>> DE2 in A64 has
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