[PATCH v3] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Dropped OHCI node and added hub model comment in EHCI. arch/arm/boot/dts/sun

[PATCH v3] ARM: sun8i: v40: enable USB host ports for Banana Pi M2 Berry

Banana Pi M2 Berry has an on-board USB Hub that provides 4 USB Type-A ports, and it's connected to the USB1 port of the SoC. Enable it. Signed-off-by: Icenowy Zheng --- Changes in v3: - Dropped OHCI node and added hub model comment in EHCI. arch/arm/boot/dts/sun8i-v40-bananapi-m2-berry.dts

[PATCH] arm64: allwinner: h6: restore the usage of CCU slice macros

As the definition of CCU slice macros are already merged into the source tree, restore the usage of the macros now. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-)

[PATCH] arm64: allwinner: h6: restore the usage of CCU slice macros

As the definition of CCU slice macros are already merged into the source tree, restore the usage of the macros now. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +++- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/arch/arm64

Re: [linux-sunxi] Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月27日 GMT+08:00 上午6:22:58, Rob Herring <r...@kernel.org> 写到: >On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote: >> >> >> 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" ><jernej.skra...@siol.net> 写到: >> >Hi all

Re: [linux-sunxi] Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月27日 GMT+08:00 上午6:22:58, Rob Herring 写到: >On Thu, Mar 22, 2018 at 02:08:43PM +0800, Icenowy Zheng wrote: >> >> >> 于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" > 写到: >> >Hi all, >> > >> >Dne sreda, 21. marec 2018 ob

Re: [linux-sunxi] Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" <jernej.skra...@siol.net> 写到: >Hi all, > >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a): >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard ><maxime.rip...@bootlin.com> >写到: &

Re: [linux-sunxi] Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月22日 GMT+08:00 上午1:13:42, "Jernej Škrabec" 写到: >Hi all, > >Dne sreda, 21. marec 2018 ob 03:18:13 CET je Icenowy Zheng napisal(a): >> 于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard > >写到: >> >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Iceno

[PATCH v2] clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU

The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Change

[PATCH v2] clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU

The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng --- Changes in v2: - Rearrange

Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote: >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC >to >> be claimed, otherwise the whole DE2 space is

Re: [PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

于 2018年3月21日 GMT+08:00 上午2:46:46, Maxime Ripard 写到: >On Sat, Mar 17, 2018 at 01:53:49AM +0800, Icenowy Zheng wrote: >> All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC >to >> be claimed, otherwise the whole DE2 space is inaccessible. >> >

[PATCH 2/2] arm64: allwinner: h6: temporarily drop the usage of CCU headers in DTSI

-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +--- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 4debc3962830..56563150d61a

[PATCH 1/2] clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU

The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drive

[PATCH 1/2] clk: sunxi-ng: add missing hdmi-slow clock for H6 CCU

The Allwinner H6 CCU has a "HDMI Slow Clock", which is currently missing in the ccu-sun50i-h6 driver. Add this missing clock to the driver. Fixes: 542353ea ("clk: sunxi-ng: add support for the Allwinner H6 CCU") Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-

[PATCH 2/2] arm64: allwinner: h6: temporarily drop the usage of CCU headers in DTSI

-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi | 20 +--- 1 file changed, 9 insertions(+), 11 deletions(-) diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi index 4debc3962830..56563150d61a 100644 --- a/arch/arm64

Re: [PATCH v4 0/9] Initial Allwinner H6 support

于 2018年3月19日 GMT+08:00 上午4:17:44, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Fri, Mar 16, 2018 at 10:02:06PM +0800, Icenowy Zheng wrote: >> This patchset adds initial support for the Allwinner H6 SoC. >> >> It's quite different from earlier Allwinner SoCs. For

Re: [PATCH v4 0/9] Initial Allwinner H6 support

于 2018年3月19日 GMT+08:00 上午4:17:44, Maxime Ripard 写到: >On Fri, Mar 16, 2018 at 10:02:06PM +0800, Icenowy Zheng wrote: >> This patchset adds initial support for the Allwinner H6 SoC. >> >> It's quite different from earlier Allwinner SoCs. For example, the >> memory map

[PATCH 6/7] arm64: allwinner: a64: add simplefb for A64 SoC

The A64 SoC features two display pipelines, one has a LCD output, the other has a HDMI output. Add support for simplefb for these pipelines on A64 SoC. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++

[PATCH 6/7] arm64: allwinner: a64: add simplefb for A64 SoC

The A64 SoC features two display pipelines, one has a LCD output, the other has a HDMI output. Add support for simplefb for these pipelines on A64 SoC. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 26 ++ 1 file changed, 26 insertions

[PATCH 5/7] arm64: allwinner: a64: add DE2 CCU related device tree nodes

As we have all necessary parts to enable the DE2 CCU on the Allwinner A64 SoC, add the needed device tree nodes, including the SRAM controller node, SRAM C node, DE2 bus node and DE2 CCU node. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dts

[PATCH 5/7] arm64: allwinner: a64: add DE2 CCU related device tree nodes

As we have all necessary parts to enable the DE2 CCU on the Allwinner A64 SoC, add the needed device tree nodes, including the SRAM controller node, SRAM C node, DE2 bus node and DE2 CCU node. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 42

[PATCH 7/7] arm64: allwinner: a64: add HDMI regulator to all DTs' simplefb_hdmi

device node. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4 arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts| 4 arch/arm64/bo

[PATCH 7/7] arm64: allwinner: a64: add HDMI regulator to all DTs' simplefb_hdmi

device node. Signed-off-by: Icenowy Zheng --- arch/arm64/boot/dts/allwinner/sun50i-a64-bananapi-m64.dts | 4 arch/arm64/boot/dts/allwinner/sun50i-a64-nanopi-a64.dts | 4 arch/arm64/boot/dts/allwinner/sun50i-a64-olinuxino.dts| 4 arch/arm64/boot/dts/allwinner/sun50i-a64

[PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC to be claimed, otherwise the whole DE2 space is inaccessible. Add a device tree binding of the DE2 part as a sub-bus. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- .../devicetree/bindings/bus/sun50i-de2-bus.txt

[PATCH 4/7] clk: sunxi-ng: add A64 compatible string

requirments, as they're processed by the parent bus driver. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i

[PATCH 3/7] bus: add bus driver for accessing Allwinner A64 DE2

egion when probing. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- drivers/bus/Kconfig | 10 ++ drivers/bus/Makefile | 1 + drivers/bus/sun50i-de2.c | 49 3 files changed, 60 insertions(+) create mode 100644 drivers/bus/su

[PATCH 2/7] dt-bindings: add binding for the Allwinner A64 DE2 bus

All the sub-blocks of Allwinner A64 DE2 needs the SRAM C on A64 SoC to be claimed, otherwise the whole DE2 space is inaccessible. Add a device tree binding of the DE2 part as a sub-bus. Signed-off-by: Icenowy Zheng --- .../devicetree/bindings/bus/sun50i-de2-bus.txt | 37

[PATCH 4/7] clk: sunxi-ng: add A64 compatible string

requirments, as they're processed by the parent bus driver. Signed-off-by: Icenowy Zheng --- drivers/clk/sunxi-ng/ccu-sun8i-de2.c | 11 --- 1 file changed, 4 insertions(+), 7 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c index 468d1abaf0ee

[PATCH 3/7] bus: add bus driver for accessing Allwinner A64 DE2

egion when probing. Signed-off-by: Icenowy Zheng --- drivers/bus/Kconfig | 10 ++ drivers/bus/Makefile | 1 + drivers/bus/sun50i-de2.c | 49 3 files changed, 60 insertions(+) create mode 100644 drivers/bus/sun50i-de2.c diff --git

[PATCH 1/7] dt-bindings: add compatible string for the A64 DE2 CCU

The Allwinner A64 SoC has a DE2 CCU like the one in the DE2 of Allwinner H5 SoC. Add a compatible string for it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devi

[PATCH 0/7] Allwinner A64 DE2 CCU support with dedicated DE2 bus driver

the bus driver. PATCH 5 is a modified version of A64 DE2 CCU patch, which uses the A64 DE2 bus. PATCH 6 and 7 are just the simplefb patches for A64. Icenowy Zheng (7): dt-bindings: add compatible string for the A64 DE2 CCU dt-bindings: add binding for the Allwinner A64 DE2 bus bus: add bus

[PATCH 1/7] dt-bindings: add compatible string for the A64 DE2 CCU

The Allwinner A64 SoC has a DE2 CCU like the one in the DE2 of Allwinner H5 SoC. Add a compatible string for it. Signed-off-by: Icenowy Zheng --- Documentation/devicetree/bindings/clock/sun8i-de2.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/clock

[PATCH 0/7] Allwinner A64 DE2 CCU support with dedicated DE2 bus driver

the bus driver. PATCH 5 is a modified version of A64 DE2 CCU patch, which uses the A64 DE2 bus. PATCH 6 and 7 are just the simplefb patches for A64. Icenowy Zheng (7): dt-bindings: add compatible string for the A64 DE2 CCU dt-bindings: add binding for the Allwinner A64 DE2 bus bus: add bus

[PATCH v4 9/9] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by:

[PATCH v4 9/9] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by: Ice

[PATCH v4 8/9] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v4 8/9] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng Reviewed

[PATCH v4 7/9] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Maxime Ripard <maxime.rip...@bootlin.com> --- Changes in v4: - Extract the device tree binding document to a

[PATCH v4 7/9] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng Acked-by: Maxime Ripard --- Changes in v4: - Extract the device tree binding document to another patch. Changes in v3: - SPDX license idetifier fix

[PATCH v4 5/9] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- No changes in v4. Changes in v3: - Rebased on newest linu

[PATCH v4 4/9] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

. The GPIO functions are dropped, as they're impossible to use -- except a GPIO only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- No changes in v4. Changes in v3: - SPDX license identifier fi

[PATCH v4 5/9] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- No changes in v4. Changes in v3: - Rebased on newest linux-next/master

[PATCH v4 4/9] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

. The GPIO functions are dropped, as they're impossible to use -- except a GPIO only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring --- No changes in v4. Changes in v3: - SPDX license identifier fix. - Dropped most GPIO functionality at PA/PB. Cha

[PATCH v4 6/9] dt-bindings: add device tree binding for Allwinner H6 main CCU

The Allwinner H6 main CCU uses the internal oscillator of the SoC, which is different with old SoCs' main CCU. Add device tree binding for the Allwinner H6 main CCU. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Extracted in v4. Documentation/devicetree/bindings/clock/sunxi-ccu.t

[PATCH v4 6/9] dt-bindings: add device tree binding for Allwinner H6 main CCU

The Allwinner H6 main CCU uses the internal oscillator of the SoC, which is different with old SoCs' main CCU. Add device tree binding for the Allwinner H6 main CCU. Signed-off-by: Icenowy Zheng --- Extracted in v4. Documentation/devicetree/bindings/clock/sunxi-ccu.txt | 4 1 file

[PATCH v4 1/9] pinctrl: sunxi: refactor irq related register function to have desc

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v4: - Adjusted parameter sequence. Patch introduced in v3. drivers/pinctrl/sunxi/p

[PATCH v4 1/9] pinctrl: sunxi: refactor irq related register function to have desc

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng --- Changes in v4: - Adjusted parameter sequence. Patch introduced in v3. drivers/pinctrl/sunxi/pinctrl-sunxi.c | 22

[PATCH v4 3/9] pinctrl: sunxi: change irq_bank_base to irq_bank_map

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng <i

[PATCH v4 2/9] pinctrl: sunxi: introduce IRQ bank conversion function

ode in IRQ register access. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Extracted in v4. drivers/pinctrl/sunxi/pinctrl-sunxi.h | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi

[PATCH v4 3/9] pinctrl: sunxi: change irq_bank_base to irq_bank_map

The Allwinner H6 SoC have its pin controllers with the first IRQ-capable GPIO bank at IRQ bank 1 and the second bank at IRQ bank 5. Change the current code that uses IRQ bank base to a IRQ bank map, in order to support the case that holes exist among IRQ banks. Signed-off-by: Icenowy Zheng

[PATCH v4 2/9] pinctrl: sunxi: introduce IRQ bank conversion function

ode in IRQ register access. Signed-off-by: Icenowy Zheng --- Extracted in v4. drivers/pinctrl/sunxi/pinctrl-sunxi.h | 23 --- 1 file changed, 12 insertions(+), 11 deletions(-) diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.h b/drivers/pinctrl/sunxi/pinctrl-sunxi.h index a1

[PATCH v4 0/9] Initial Allwinner H6 support

controller is broken), and the second one with USB 3.0 (the first one is A80). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (9): pinctrl: sunxi: refactor irq related register function to have desc

[PATCH v4 0/9] Initial Allwinner H6 support

controller is broken), and the second one with USB 3.0 (the first one is A80). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (9): pinctrl: sunxi: refactor irq related register function to have desc

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec" 写到: >Hi Julian, > >Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby >napisal(a): >> Hi Jernej, >> >> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec > >wrote: >> > Enable HDMI

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月27日 GMT+08:00 上午12:16:44, "Jernej Škrabec" 写到: >Hi Julian, > >Dne nedelja, 25. februar 2018 ob 09:11:34 CET je Julian Calaby >napisal(a): >> Hi Jernej, >> >> On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec > >wrote: >> > Enable HDMI output on all boards which have HDMI connector. >>

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月25日 GMT+08:00 下午5:06:32, Julian Calaby <julian.cal...@gmail.com> 写到: >Hi Icenowy, > >On Sun, Feb 25, 2018 at 7:43 PM, Icenowy Zheng <icen...@aosc.io> wrote: >> >> >> 于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby ><julian.cal...@gmail.com&g

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月25日 GMT+08:00 下午5:06:32, Julian Calaby 写到: >Hi Icenowy, > >On Sun, Feb 25, 2018 at 7:43 PM, Icenowy Zheng wrote: >> >> >> 于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby > 写到: >>>Hi Jernej, >>> >>>On Sun, Feb 25, 2018 at 8

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby 写到: >Hi Jernej, > >On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec > wrote: >> Enable HDMI output on all boards which have HDMI connector. >> >> Signed-off-by: Jernej Skrabec

Re: [linux-sunxi] [PATCH 14/15] ARM: dts: sun8i: h3: Enable HDMI output on H3 boards

于 2018年2月25日 GMT+08:00 下午4:11:34, Julian Calaby 写到: >Hi Jernej, > >On Sun, Feb 25, 2018 at 8:45 AM, Jernej Skrabec > wrote: >> Enable HDMI output on all boards which have HDMI connector. >> >> Signed-off-by: Jernej Skrabec >> --- >> arch/arm/boot/dts/sun8i-h3-bananapi-m2-plus.dts| 25

Re: [PATCH v3 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

于 2018年2月23日 GMT+08:00 下午11:20:38, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote: >> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with >its >> memory map fully reworked and some high-spee

Re: [PATCH v3 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

于 2018年2月23日 GMT+08:00 下午11:20:38, Maxime Ripard 写到: >On Fri, Feb 23, 2018 at 08:35:54PM +0800, Icenowy Zheng wrote: >> Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with >its >> memory map fully reworked and some high-speed peripherals (PCIe, USB

[PATCH v3 7/7] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by:

[PATCH v3 7/7] arm64: allwinner: h6: add support for Pine H64 board

and "Expansion" pin header - 2 USB 2.0 ports and 1 USB 3.0 ports - Audio jack - MicroSD slot and eMMC module slot - on-board SPI NOR flash - 1Gbps Ethernet port (via RTL8211E PHY) - HDMI port Adds initial support for it, including the UART on the Expansion pin header. Signed-off-by: Ice

[PATCH v3 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v3 6/7] arm64: allwinner: h6: add the basical Allwinner H6 DTSI file

Allwinner H6 is a new SoC with Cortex-A53 cores from Allwinner, with its memory map fully reworked and some high-speed peripherals (PCIe, USB 3.0) introduced. This commit adds the basical DTSI file of it, including the clock support and UART support. Signed-off-by: Icenowy Zheng Reviewed

[PATCH v3 5/7] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng <icen...@aosc.io> Acked-by: Rob Herring <r...@kernel.org> --- Changes in v3: - SPDX license idetifier fix. - Add some comments at in

[PATCH v3 5/7] clk: sunxi-ng: add support for the Allwinner H6 CCU

The Allwinner H6 SoC has a CCU which has been largely rearranged. Add support for it in the sunxi-ng CCU framework. Signed-off-by: Icenowy Zheng Acked-by: Rob Herring --- Changes in v3: - SPDX license idetifier fix. - Add some comments at initialization. Changes in v2: - Exported APB1 bus

[PATCH v3 4/7] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - Rebased on newest linux-next/

[PATCH v3 4/7] clk: sunxi-ng: Support fixed post-dividers on NKMP style clocks

On the new Allwinner H6 SoC, multiple PLL's are NMP style clocks (modelled as NKMP with no K) and have fixed post-dividers. Add fixed post divider support to the NKMP style clocks. Signed-off-by: Icenowy Zheng --- Changes in v3: - Rebased on newest linux-next/master. No changes in v2

[PATCH v3 2/7] pinctrl: sunxi: support pin controllers with holes among IRQ banks

to hardware IRQ bank map, so the new situation in H6 main pin controller can be processed. The old special situation which uses a constant offset (on A33 and V3s, both with a offset of 1) can be also processed with the new code. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: -

[PATCH v3 2/7] pinctrl: sunxi: support pin controllers with holes among IRQ banks

to hardware IRQ bank map, so the new situation in H6 main pin controller can be processed. The old special situation which uses a constant offset (on A33 and V3s, both with a offset of 1) can be also processed with the new code. Signed-off-by: Icenowy Zheng --- Changes in v3: - change for the refactor

[PATCH v3 3/7] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

. The GPIO functions are dropped, as they're impossible to use -- except a GPIO only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v3: - SPDX license identifier fix. - Dropped most GPIO functionality at PA/PB. Changes in v2: - Dropped

[PATCH v3 3/7] pinctrl: sunxi: add support for the Allwinner H6 main pin controller

. The GPIO functions are dropped, as they're impossible to use -- except a GPIO only pin (PB20) which might be the IRQ of ATE. Signed-off-by: Icenowy Zheng --- Changes in v3: - SPDX license identifier fix. - Dropped most GPIO functionality at PA/PB. Changes in v2: - Dropped without_bus_gate d

[PATCH v3 1/7] pinctrl: sunxi: refactor irq related register function to have desc

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- New patch in v3. drivers/pinctrl/sunxi/pinctrl-sunxi.c | 18 -- drivers/pinctrl

[PATCH v3 1/7] pinctrl: sunxi: refactor irq related register function to have desc

As the new H6 SoC has holes in the IRQ registers, refactor the IRQ related register function for getting the full pinctrl desc structure. Signed-off-by: Icenowy Zheng --- New patch in v3. drivers/pinctrl/sunxi/pinctrl-sunxi.c | 18 -- drivers/pinctrl/sunxi/pinctrl-sunxi.h | 29

[PATCH v3 0/7] Initial Allwinner H6 support

). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (7): pinctrl: sunxi: refactor irq related register function to have desc pinctrl: sunxi: support pin controllers with holes among IRQ banks pinctrl

[PATCH v3 0/7] Initial Allwinner H6 support

). This patchset adds the most basical support for it, including the main pin controller, the main CCU and the basical device tree. Icenowy Zheng (7): pinctrl: sunxi: refactor irq related register function to have desc pinctrl: sunxi: support pin controllers with holes among IRQ banks pinctrl

[PATCH v5] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v5] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng --- Changes in v5

Re: [PATCH v4] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

在 2018-02-08 17:00，Maxime Ripard 写道： On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote: Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM

Re: [PATCH v4] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

在 2018-02-08 17:00，Maxime Ripard 写道： On Tue, Feb 06, 2018 at 09:16:47PM +0800, Icenowy Zheng wrote: Banana Pi M2 Zero board is a H2+-based board by Sinovoip, with a form factor and GPIO holes similar to Raspberry Pi Zero. It features: - Allwinner H2+ SoC - Single-chip (16-bit) 512MiB DDR3 DRAM

Re: [PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU

于 2018年2月7日 GMT+08:00 下午5:02:10, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >Hi, > >On Sat, Feb 03, 2018 at 11:49:40PM +0800, Icenowy Zheng wrote: >> +/* Force the output divider of video PLLs to 0 */ >> +for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++)

Re: [PATCH v2 4/6] clk: sunxi-ng: add support for the Allwinner H6 CCU

于 2018年2月7日 GMT+08:00 下午5:02:10, Maxime Ripard 写到: >Hi, > >On Sat, Feb 03, 2018 at 11:49:40PM +0800, Icenowy Zheng wrote: >> +/* Force the output divider of video PLLs to 0 */ >> +for (i = 0; i < ARRAY_SIZE(pll_video_regs); i++) { >> +val

[PATCH v4] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng <icen...@aosc

[PATCH v4] ARM: sun8i: h2+: add support for Banana Pi M2 Zero board

to power the board and the other features OTG functionality) - Two keys, a reset and a GPIO-connected key. - HDMI Type-C (miniHDMI) connector connected to the HDMI part of H2+. - CSI connector to connect the camera sensor provided by Sinovoip. Signed-off-by: Icenowy Zheng --- Changes in v4

Re: [PATCH v2 05/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

于 2018年2月6日 GMT+08:00 下午5:06:56, Maxime Ripard <maxime.rip...@bootlin.com> 写到: >On Tue, Feb 06, 2018 at 12:49:00PM +0800, Icenowy Zheng wrote: >> The CPU on Allwinner H3 can do dynamic frequency scaling. >> >> Add a DVFS table based on the one shipped with Allwinne

Re: [PATCH v2 05/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

于 2018年2月6日 GMT+08:00 下午5:06:56, Maxime Ripard 写到: >On Tue, Feb 06, 2018 at 12:49:00PM +0800, Icenowy Zheng wrote: >> The CPU on Allwinner H3 can do dynamic frequency scaling. >> >> Add a DVFS table based on the one shipped with Allwinner's H3 SDK. >The >> voltag

[PATCH v2 07/10] ARM: sun8i: h3: add SY8113B regulator used by Orange Pi One board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- New patch in v2. arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/ar

[PATCH v2 07/10] ARM: sun8i: h3: add SY8113B regulator used by Orange Pi One board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng --- New patch in v2. arch/arm/boot/dts/sun8i-h3-orangepi-one.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h3-orangepi-one.dts b/arch/arm/boot/dts/sun8i-h3

[PATCH v2 08/10] ARM: sun8i: h3: Add SY8106A regulator to Orange Pi PC

From: Ondrej Jirman <meg...@megous.com> Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on Orange Pi PC, then set the power supply of the ARM cores to this regulator, in order to enable DVFS. Signed-off-by: Ondrej Jirman <meg...@megous.com> [Icenowy: Enable DVFS in this p

[PATCH v2 08/10] ARM: sun8i: h3: Add SY8106A regulator to Orange Pi PC

From: Ondrej Jirman Add SY8106A regulator to r_i2c bus and enable the r_i2c bus on Orange Pi PC, then set the power supply of the ARM cores to this regulator, in order to enable DVFS. Signed-off-by: Ondrej Jirman [Icenowy: Enable DVFS in this patch, slight changes and change commit message

[PATCH v2 10/10] ARM: sun8i: h3: set the cpu-supply to VDD-CPUX on ALL-H3-CC H3 ver

The ALL-H3-CC has a fixed VDD-CPUX voltage at 1.2V, which is supplied by a regulator. Set the CPU's cpu-supply property to the VDD-CPUX regulator. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- New patch in v2. arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 4 1 file chan

[PATCH v2 10/10] ARM: sun8i: h3: set the cpu-supply to VDD-CPUX on ALL-H3-CC H3 ver

The ALL-H3-CC has a fixed VDD-CPUX voltage at 1.2V, which is supplied by a regulator. Set the CPU's cpu-supply property to the VDD-CPUX regulator. Signed-off-by: Icenowy Zheng --- New patch in v2. arch/arm/boot/dts/sun8i-h3-libretech-all-h3-cc.dts | 4 1 file changed, 4 insertions

[PATCH v2 06/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- No changes in v2. arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-ze

[PATCH v2 06/10] ARM: sun8i: h2+: add SY8113B regulator used by Orange Pi Zero board

of this regulator and set the cpu's cpu-supply property to it. Signed-off-by: Icenowy Zheng --- No changes in v2. arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts | 21 + 1 file changed, 21 insertions(+) diff --git a/arch/arm/boot/dts/sun8i-h2-plus-orangepi-zero.dts b/arch/arm/boot

[PATCH v2 05/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

, and 1.3V (the highest VDD-CPUX voltage suggested by the datasheet) as the maximum allowed value. It's proven to work well with a board with SY8113B. Signed-off-by: Icenowy Zheng <icen...@aosc.io> --- Changes in v2: - Switch to BSP OPP table, which is more conservative. arch/arm/boot/dts/sun8i-h

[PATCH v2 05/10] ARM: sun8i: h3: add operating-points-v2 table for CPU

, and 1.3V (the highest VDD-CPUX voltage suggested by the datasheet) as the maximum allowed value. It's proven to work well with a board with SY8113B. Signed-off-by: Icenowy Zheng --- Changes in v2: - Switch to BSP OPP table, which is more conservative. arch/arm/boot/dts/sun8i-h3.dtsi | 32

[PATCH v2 09/10] ARM: sun8i: h3: fix ALL-H3-CC H3 ver VDD-CPUX voltage

The VDD-CPUX voltage of ALL-H3-CC H3 ver should be 1.2V, not the 3.3V currently defined in the device tree. Fix the voltage in the device tree. Fixes: 6ca358645d4d ("ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.") Signed-off-by: Icenowy Zheng <ic

[PATCH v2 09/10] ARM: sun8i: h3: fix ALL-H3-CC H3 ver VDD-CPUX voltage

The VDD-CPUX voltage of ALL-H3-CC H3 ver should be 1.2V, not the 3.3V currently defined in the device tree. Fix the voltage in the device tree. Fixes: 6ca358645d4d ("ARM: dts: sun8i: h3: Add dts file for Libre Computer Board ALL-H3-CC H3 ver.") Signed-off-by: Icenowy Zheng --- New p

<    1   2   3   4   5   6   7   8   9   10   >