age to take another stab.
~Joshua
On Wed, Sep 18, 2019 at 11:35 AM Benjamin Tissoires
wrote:
>
> On Thu, Aug 29, 2019 at 1:26 AM Joshua Clayton
> wrote:
> >
> > ping?
> > I'd love to see this get in.
> > with distro kernel I have effectively no dmesg due to
ping?
I'd love to see this get in.
with distro kernel I have effectively no dmesg due to this issue
On Mon, Aug 12, 2019 at 9:20 AM wrote:
>
> From: Joshua Clayton
>
> Only warn once of oversize hid report value field
>
> On HP spectre x360 convertible the message:
>
On Mon, Jul 22, 2019 at 3:30 PM Joe Perches wrote:
>
> On Mon, 2019-07-22 at 15:26 -0600, stillcompil...@gmail.com wrote:
> > From: Joshua Clayton
>
> Thanks Joshua
>
> > On HP spectre x360 convertible the message:
> > hid-sensor-hub 001F:8087:0AC2.0002: hid_f
On Mon, Jul 22, 2019 at 11:23 AM Joe Perches wrote:
>
> On Mon, 2019-07-22 at 10:36 -0600, stillcompil...@gmail.com wrote:
> > On HP spectre x360 convertible the message:
> > hid-sensor-hub 001F:8087:0AC2.0002: hid_field_extract() called with n (192)
> > > 32! (kworker/1:2)
> > is continually pri
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.
Signed-off-by: Josh
Add support for Altera FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index
-by: Joshua Clayton
---
Changes since v12:
- Change "depends on SPI || COMPILE_TEST" to "depends on SPI" in patch 3
include/linux/fpga/fpga-mgr.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index b4ac24
Speed up bit reversal by using hardware bit reversal
Add extra code to handle less than 4byte remnants, if any
Signed-off-by: Joshua Clayton
---
drivers/fpga/altera-ps-spi.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/altera-ps-spi.c b
Describe an altera-passive-serial devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
---
.../bindings/fpga/altera-passive-serial.txt| 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.
Signed-off-by: Joshua Clayton
---
include/linux/bitrev.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.
Signed-off-by: Josh
Speed up bit reversal by using hardware bit reversal
Add extra code to handle less than 4byte remnants, if any
Signed-off-by: Joshua Clayton
---
drivers/fpga/altera-ps-spi.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/altera-ps-spi.c b
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.
Signed-off-by: Joshua Clayton
---
include/linux/bitrev.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index
Add support for Altera FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index
Describe an altera-passive-serial devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
---
.../bindings/fpga/altera-passive-serial.txt| 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings
-by: Joshua Clayton
---
Changes from v11 (all in patch 4/4)
- Change "Altera V FPGA" to simply "Altera FPGA"
- Change the devicetree name to a generic "fpga: fpga@0"
from "fpga_spi: cyclonespi@0"
include/linux/fpga/fpga-mgr.h | 2 ++
1 file changed, 2 i
-by: Joshua Clayton
---
include/linux/fpga/fpga-mgr.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/include/linux/fpga/fpga-mgr.h b/include/linux/fpga/fpga-mgr.h
index b4ac24c4411d..01c348ca38b7 100644
--- a/include/linux/fpga/fpga-mgr.h
+++ b/include/linux/fpga/fpga-mgr.h
@@ -67,10 +67,12
Speed up bit reversal by using hardware bit reversal
Add extra code to handle less than 4byte remnants, if any
Signed-off-by: Joshua Clayton
---
drivers/fpga/altera-ps-spi.c | 19 +++
1 file changed, 15 insertions(+), 4 deletions(-)
diff --git a/drivers/fpga/altera-ps-spi.c b
Describe an altera-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
Signed-off-by: Anatolij Gustschin
---
.../bindings/fpga/altera-passive-serial.txt| 29 ++
1 file changed, 29 insertions(+)
create mode 100644
altera-ps-spi loads FPGA firmware over SPI, using the "passive serial"
interface on Altera Arria 10, Cyclone V or Stratix V FPGAs.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional SPI with lsb first.
Signed-off-by: Josh
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.
Signed-off-by: Joshua Clayton
---
include/linux/bitrev.h | 19 +++
1 file changed, 19 insertions(+)
diff --git a/include/linux/bitrev.h b/include/linux/bitrev.h
index
Add support for Altera V FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index
ze buffer.
Anatolij Gustschin (1):
fpga: Add flag to indicate SPI bitstream is bit-reversed
Joshua Clayton (4):
doc: dt: add altera-ps-spi binding document
fpga manager: Add altera-ps-spi driver for Altera FPGAs
ARM: dts: imx6q-evi: support altera-ps-spi
lib: add bitrev8x4()
fpga-manager
Hi Alanatolij,
I was just finally able to test this and your other change yesterday
On Thursday, April 20, 2017 11:43:01 PM PDT Anatolij Gustschin wrote:
> Add a flag that is passed to the write_init() callback,
> indicating that the SPI bitstream starts with LSB first.
> SPI controllers usual
ad of a 1k buffer on the
stack, it calls fdt_appendprop_string()
Signed-off-by: Joshua Clayton
---
I tried testing this on my imx6 setup by adding bogus text to the
command line, but it appears that with my (recent) uboot
the codepath is not executed.
So this could be regarded as little more th
On 02/15/2017 09:14 AM, Alan Tull wrote:
> On Wed, Feb 15, 2017 at 9:26 AM, Anatolij Gustschin wrote:
>> Hi Joshua,
>>
>> On Tue, 24 Jan 2017 14:19:33 -0800
>> Joshua Clayton stillcompil...@gmail.com wrote:
>> ...
>>> +static int cyclonespi_write
Thanks, Rob.
On 01/27/2017 02:28 PM, Rob Herring wrote:
> On Tue, Jan 24, 2017 at 02:19:32PM -0800, Joshua Clayton wrote:
>> Describe a cyclone-ps-spi devicetree entry, required features
>>
>> Signed-off-by: Joshua Clayton
>> ---
>> .../bindings/fpga/alte
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Add support for Altera cyclone V FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/altera-passive-serial.txt| 29 ++
1 file changed, 29 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
>From c429cec34a880c0d5438091f436a5946a4db3fc0 Mon Sep 17 00:00:00 2001
Message-Id:
From: Joshua Clayton
Date: Mon, 23 Jan 2017 14:43:20 -0800
Subject: [PATCH v8 0/3] Altera Cyclone Passive Serial SPI FPGA Manager
This series adds an FPGA manager for Altera cyclone FPGAs
that can program t
On 01/23/2017 04:00 PM, Fabio Estevam wrote:
> On Mon, Jan 23, 2017 at 8:51 PM, Joshua Clayton
> wrote:
>> Add support for Altera cyclone V FPGA connected to an spi port
>> to the evi devicetree file
>>
>> Signed-off-by: Joshua Clayton
>> ---
>
oduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (3):
doc: dt: add cyclone-ps-spi binding document
fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
ARM: dts
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Add support for Altera cyclone V FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
---
.../bindings/fpga/altera-passive-serial.txt| 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga
Running sparse on this subdirectory suggested __fpga_mgr_get()
should be static.
__fpga_mgr_get() is internal to the fpga-mgr framework.
Define it as static
Signed-off-by: Joshua Clayton
---
drivers/fpga/fpga-mgr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/fpga
t;
> url:
> https://github.com/0day-ci/linux/commits/Joshua-Clayton/Altera-Cyclone-Passive-Serial-SPI-FPGA-Manager/20170120-172349
> reproduce:
> # apt-get install sparse
> make ARCH=x86_64 allmodconfig
> make C=1 CF=-D__CHECK_ENDIAN__
>
Add support for Altera cyclone V FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
ping into cyclonespi_write(), as requested.
This falls short of my desired generic lsb first spi support, but is a step
in that direction.
- Fixed whitespace problems introduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/altera-passive-serial.txt| 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/altera-passive-serial.txt
Uwe,
Thanks so much for your review.
On 12/18/2016 11:23 PM, Uwe Kleine-König wrote:
> On Fri, Dec 16, 2016 at 03:17:53PM -0800, Joshua Clayton wrote:
>> cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
>> interface on Altera Cyclone FPGAS.
>>
Will,
On 12/19/2016 02:06 AM, Will Deacon wrote:
> On Fri, Dec 16, 2016 at 03:17:51PM -0800, Joshua Clayton wrote:
>> Implement faster bitrev8x4() for arm, arm64 and mips, all the platforms
>> with CONFIG_HAVE_ARCH_BITREVERSE.
>> ARM platforms just need a byteswap
__arch_bitrev32()
Signed-off-by: Joshua Clayton
---
arch/arm/include/asm/bitrev.h | 6 ++
arch/arm64/include/asm/bitrev.h | 6 ++
arch/mips/include/asm/bitrev.h | 6 ++
include/linux/bitrev.h | 1 +
4 files changed, 19 insertions(+)
diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga
Add support for Altera cyclone V FPGA connected to an spi port
to the evi devicetree file
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
Add a function to reverse bytes within a 32 bit word.
Operate on a u32 rather than individual bytes.
ARCH specific versions require substantially fewer instructions than
working a byte at a time.
Signed-off-by: Joshua Clayton
---
include/linux/bitrev.h | 25 +
1 file
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (5):
lib: add bitrev8x4()
lib: implement __arch_bitrev8x4()
doc: dt: add cyclone-ps-spi binding document
fpga manager: Add cy
space problems introduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (3):
lib: add bitrev8x4()
doc: dt: add cyclone-ps-spi binding document
fpga manager: Add cyclone
:04:40 -0800
> Joshua Clayton stillcompil...@gmail.com wrote:
> ...
>> +static int cyclonespi_write_init(struct fpga_manager *mgr, u32 flags,
>> + const char *buf, size_t count)
> there is a minor API change in linux-next [1]. struct fpga_image_info
Describe a cyclone-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
Acked-by: Rob Herring
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Add a function to reverse bytes within a 32 bit word.
This function is more efficient than using the 8 bit version when
iterating over an array
Signed-off-by: Joshua Clayton
---
arch/arm/include/asm/bitrev.h | 6 ++
include/linux/bitrev.h| 26 ++
2 files
Hello Anatolij,
Thanks for the review.
On 12/01/2016 02:45 PM, Anatolij Gustschin wrote:
> On Thu, 1 Dec 2016 09:04:50 -0800
> Joshua Clayton stillcompil...@gmail.com wrote:
> ...
>> diff --git a/arch/arm/include/asm/bitrev.h b/arch/arm/include/asm/bitrev.h
>> index ec
Describe a cyclonei-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 25 ++
1 file changed, 25 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Add a function to reverse bytes within a 32 bit word.
This function is more efficient than using the 8 bit version when
iterating over an array
Signed-off-by: Joshua Clayton
---
Looking for an ACK from Russell King on this patch (or at least
the arm specific implementation)
arch/arm/include
oduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (3):
lib: add bitrev8x4()
doc: dt: add cyclone-spi binding document
fpga manager: Add cyclone-ps-spi driver for Al
Hi Alan,
On 11/30/2016 09:45 AM, atull wrote:
> On Wed, 30 Nov 2016, Joshua Clayton wrote:
>
> Hi Clayton,
>
> I just have a few minor one line changes below. Only one
> is operational, I should have caught that earlier.
>
Thanks for the speedy review.
>> +};
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Describe a cyclonei-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga
Add a function to reverse bytes within a 32 bit word.
This function is more efficient than using the 8 bit version when
iterating over an array
Signed-off-by: Joshua Clayton
---
arch/arm/include/asm/bitrev.h | 5 +
include/linux/bitrev.h| 26 ++
2 files
r for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (3):
lib: add bitrev8x4()
doc: dt: add cyclone-spi binding document
fpga manager: Add cyclone-ps-spi driver for Altera FPGAs
.../bindings/fpga/cyclone-ps-spi
imx-weim should always set address-cells to 2,
and size_cells to 1.
On imx6, fsl,weim-cs-gpr will always be &gpr
Set these common parameters in the dtsi file,
rather than in a downstream dts.
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 3 ---
arch/arm/boot
information]
>
> url:
> https://github.com/0day-ci/linux/commits/Joshua-Clayton/lib-add-bitrev8x4/20161029-012535
> config: openrisc-allmodconfig (attached as .config)
> compiler: or32-linux-gcc (GCC) 4.5.1-or32-1.0rc1
> reproduce:Dang it!
> wget
> https://git.kern
for review, though.
>
> On Fri, Oct 28, 2016 at 09:56:42AM -0700, Joshua Clayton wrote:
>> The status pin may not show ready in the time described in the
>> Altetera manual. check the value several times before giving up
> s/Altetera/Altera
Thanks. I'll fix this. And it wi
Describe a cyclonei-ps-spi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/cyclone-ps-spi-fpga-mgr.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/cyclone-ps-spi-fpga
cyclone-ps-spi loads FPGA firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
This is one of the simpler ways to set up an FPGA at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fp
Add support for Altera cyclone V FPGA connected to an spi port
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 6de21ff..bd0b85c 100644
direction.
- Fixed whitespace problems introduced during refactoring
- Replaced magic number for initial delay with a descriptive macro
- Poll the fpga to see when it is ready rather than a fixed 1 ms sleep
Joshua Clayton (5):
lib: add bitrev8x4()
doc: dt: add cyclone-spi binding document
fpga
The status pin may not show ready in the time described in the
Altetera manual. check the value several times before giving up
For the hardware I am working on, the status pin takes 250 us,
5 times as long as described by Altera.
Signed-off-by: Joshua Clayton
---
drivers/fpga/cyclone-ps-spi.c
Add a function to reverse bytes within a 32 bit word.
This function is more efficient than using the 8 bit version when
iterating over an array
Signed-off-by: Joshua Clayton
---
arch/arm/include/asm/bitrev.h | 5 +
include/linux/bitrev.h| 26 ++
2 files
f_load the whole image buffer at once. But it is easy to
> imagine that some time in the future we may want to expand the FPGA
> manager API to support streaming where we don't have the whole buffer.
OK.
If generic lsb first support for SPI is too high a bar (which it may be),
I will move the bit reversing code into the write function.
> Thanks for submitting, Joshua. Will be looking at this over the
> next several days.
>
> Alan
Thanks for the quick response!
I'll be looking forward to your review,
Joshua Clayton
Moritz,
thank you very much for the review.
On 10/06/2016 07:53 PM, Moritz Fischer wrote:
> Hi Joshua,
>
> On Thu, Oct 6, 2016 at 1:34 PM, Joshua Clayton
> wrote:
>> Describe a cyclonespi devicetree entry, required features
>>
>> Signed-off-by: Joshua Clayton
Describe a cyclonespi devicetree entry, required features
Signed-off-by: Joshua Clayton
---
.../bindings/fpga/cyclone-spi-fpga-mgr.txt | 23 ++
1 file changed, 23 insertions(+)
create mode 100644
Documentation/devicetree/bindings/fpga/cyclone-spi-fpga-mgr.txt
diff
cyclonespi loads fpga firmware over spi, using the "passive serial"
interface on Altera Cyclone FPGAS.
one of the simpler ways to set up an fpga at runtime.
The signal interface is close to unidirectional spi with lsb first.
Signed-off-by: Joshua Clayton
---
drivers/fpga/Kconfig
Add support for Altera cyclone V FPGA connected to an spi port
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 16
1 file changed, 16 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 6de21ff..7e5d3cf 100644
On Monday, September 05, 2016 09:11:47 AM Quentin Schulz wrote:
> On 05/09/2016 09:07, Maxime Ripard wrote:
> > Hi,
> >
> > Nitpicks ahead.
> >
> > On Thu, Sep 01, 2016 at 04:05:05PM +0200, Quentin Schulz wrote:
> >> + info->soc_specific = (struct soc_specific
> >> *)platform_get_device_id(pdev
chip */
> +/* There's an off-by-one between the gpio bank number and the gpiochip */
> /* range e.g. GPIO_1_5 is gpio 5 under linux */
> #define IMX_GPIO_NR(bank, nr)(((bank) - 1) * 32 + (nr))
>
>
That's Betterer! ;)
Reviewed-by Joshua Clayton
On Thursday, September 01, 2016 10:48:16 PM Martin Kaiser wrote:
> Signed-off-by: Martin Kaiser
> ---
> arch/arm/mach-imx/hardware.h |2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/mach-imx/hardware.h b/arch/arm/mach-imx/hardware.h
> index a42a6df..2810ffc 10
Hi Peter,
On 08/11/2016 08:11 PM, Peter Chen wrote:
> On Thu, Aug 11, 2016 at 09:40:32AM -0700, Joshua Clayton wrote:
>> Previously the onboard hub was made to work by treating its
>> reset gpio as a regulator enable.
>> Get rid of that kludge now that pwseq has added reset
Apply hardware workaround for ethernet problem
See nxp erratum err006687
Signed-off-by: Joshua Clayton
---
Changed since V1:
- added fsl,err006687-workaround-present; so that it will continue to work
arch/arm/boot/dts/imx6q-evi.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch
Stefan,
On 08/11/2016 10:09 AM, Stefan Wahren wrote:
> Hi Joshua,
>
>> Joshua Clayton hat am 11. August 2016 um 18:54
>> geschrieben:
>>
>>
>> Apply hardware workaround for ethernet problem
>> See nxp erratum err006687
> do you know this commit?
>
Battery capacity level is a standard feature of sbs battery
That can be used to tell what the remainig battery capacity is, and
can tell if the battery has not been calibrated/initialized, which makes
the capacity and charging/discharging percentages invalid.
Signed-off-by: Joshua Clayton
Apply hardware workaround for ethernet problem
See nxp erratum err006687
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts b/arch/arm/boot/dts/imx6q-evi.dts
index 49c6f61..33bd04b 100644
--- a
From: Peter Chen
The current dts describes USB HUB's property at USB controller's
entry, it is improper. The USB HUB should be the child node
under USB controller, and power sequence properties are under
it.
Signed-off-by: Peter Chen
Signed-off-by: Joshua Clayton
---
arch/ar
Hi Peter,
Consider this my attempt to squeeze my own dts into your patch series.
These patches repalce patch 6 in V5. of the usb pwrseq series
I adding a #address and #size to imx6qdl.dtsi in patch 1
and remove those lines from imx6qdl-udoo.dtsi in patch 2 (formerly patch 6)
Finally I make the ch
Give usb nodes #address and #size attributes, so that a child node
representing a permanently connected device such as an onboard hub may
be addressed with a attribute
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6qdl.dtsi | 6 ++
1 file changed, 6 insertions(+)
diff --git a
Previously the onboard hub was made to work by treating its
reset gpio as a regulator enable.
Get rid of that kludge now that pwseq has added reset gpio support
Move pin muxing the hub reset pin into the usbh1 group
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 25
Hi Peter,
On 08/08/2016 01:52 AM, Peter Chen wrote:
> The current dts describes USB HUB's property at USB controller's
> entry, it is improper. The USB HUB should be the child node
> under USB controller, and power sequence properties are under
> it.
>
> Signed-off-by: Peter Chen
> ---
> arch/ar
On 07/28/2016 09:41 AM, Fabio Estevam wrote:
> Hi Joshua,
>
> On Thu, Jul 28, 2016 at 12:56 PM, Joshua Clayton
> wrote:
>
>> I assume there is a v4 coming due to rmk's comments on patch 5.
>> I couldn't figure out where to null the of_node in error paths, bu
Peter,
On 07/27/2016 06:45 PM, Peter Chen wrote:
> On Wed, Jul 27, 2016 at 09:25:11AM -0700, Joshua Clayton wrote:
>> Patch 4 does not apply for me
>> (The Makefile has a "usbcore-$(CONFIG_OF) += of.o"
>> line which I don't see in 4.7 or linux/next master)
ings/power/pwrseq/pwrseq-generic.txt
> create mode 100644 drivers/power/pwrseq/Kconfig
> create mode 100644 drivers/power/pwrseq/Makefile
> create mode 100644 drivers/power/pwrseq/core.c
> create mode 100644 drivers/power/pwrseq/pwrseq_generic.c
> create mode 100644 drivers/usb/
On 07/20/2016 02:40 AM, Peter Chen wrote:
> Some hard-wired USB devices need to do power sequence to let the
> device work normally, the typical power sequence like: enable USB
> PHY clock, toggle reset pin, etc. But current Linux USB driver
> lacks of such code to do it, it may cause some hard-w
Greetings Guenter,
Thank you for reviewing my submission.
On 07/15/2016 06:40 PM, Guenter Roeck wrote:
> On 07/15/2016 05:18 PM, Joshua Clayton wrote:
>> Add new driver for Texas Instruments ADS1118 and and ADS1018.
>> This driver works with ADS1018, because of code borrowed
On Sunday, July 17, 2016 03:34:25 PM Rob Herring wrote:
> On Fri, Jul 15, 2016 at 05:18:22PM -0700, Joshua Clayton wrote:
> > ads1118 is a 4 input 16 bit adc with a buit-in temperature gauge
> >
> > Signed-off-by: Joshua Clayton
> > ---
> > .../devi
Add new driver for Texas Instruments ADS1118 and and ADS1018.
This driver works with ADS1018, because of code borrowed
from asd1015, which is similar, but I can only test ADS1118
Signed-off-by: Joshua Clayton
---
drivers/hwmon/Kconfig | 11 ++
drivers/hwmon/Makefile | 1 +
drivers/hwmon
add support to imx6q-evi for the 3 ADS1118 temperature/adc units,
now that is has has a kernel driver
Signed-off-by: Joshua Clayton
---
arch/arm/boot/dts/imx6q-evi.dts | 90 +
1 file changed, 90 insertions(+)
diff --git a/arch/arm/boot/dts/imx6q-evi.dts
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