Ping...
On 2020/12/3 22:16, Wei Li wrote:
> Armv8.3 extends the SPE by adding:
> - Alignment field in the Events packet, and filtering on this event
> using PMSEVFR_EL1.
> - Support for the Scalable Vector Extension (SVE).
>
> The main additions for SVE are:
> - Recording the vector length for
Hi,
On 2020/11/25 18:11, Tiezhu Yang wrote:
> After commit 9cce844abf07 ("MIPS: CPU#0 is not hotpluggable"),
Why CPU#0 is not hotpluggable on MIPS? Does that unrealizable?
> c->hotpluggable is 0 for CPU 0 and it will not generate a control
> file in sysfs for this CPU:
>
> [root@linux
Hi Will,
On 2020/11/30 18:06, Will Deacon wrote:
> On Fri, Nov 27, 2020 at 02:03:22PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
Hi Yang,
On 2020/11/25 6:13, Li Yang wrote:
> On Tue, Nov 24, 2020 at 3:44 PM Li Yang wrote:
>>
>> On Tue, Nov 24, 2020 at 12:24 AM Wei Li wrote:
>>>
>>> IS_ERR_VALUE macro should be used only with unsigned long type.
>>> Especially it works incorrectly with unsigned shorter types on
>>> 64bit
Hi Will,
On 2020/10/2 18:57, Will Deacon wrote:
> On Wed, Sep 30, 2020 at 05:31:35PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
Hi Will,
On 2020/9/7 20:51, Will Deacon wrote:
> On Fri, Jul 24, 2020 at 05:16:04PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
>>
Hi Andi,
On 2020/9/23 3:50, Andi Kleen wrote:
> On Tue, Sep 22, 2020 at 12:23:21PM -0700, Andi Kleen wrote:
>>> After debugging, i found the root reason is that the xyarray fd is created
>>> by evsel__open_per_thread() ignoring the cpu passed in
>>> create_perf_stat_counter(), while the evsel'
Hi Namhyung,
On 2020/9/17 13:19, Namhyung Kim wrote:
> Hello,
>
> On Thu, Sep 17, 2020 at 11:45 AM Wei Li wrote:
>>
>> Since we have introduced map_for_each_event() to walk the 'pmu_events_map',
>> clean up metricgroup__print() and metricgroup__has_metric() with it.
>>
>> Signed-off-by: Wei Li
Hi luobin,
On 2020/9/17 11:44, luobin (L) wrote:
> On 2020/9/17 11:03, Wei Li wrote:
>> +err = irq_set_affinity_hint(rq->irq, >affinity_mask);
>> +if (err)
>> +goto err_irq;
>> +
>> +return 0;
>> +
>> +err_irq:
>> +rx_del_napi(rxq);
>> +return err;
> If
Hi Leo,
On 2020/8/7 15:16, Leo Yan wrote:
> This patch introduces two new APIs, one is to calculate from converting
> counter to timestamp and provides a reverse flow to convert timestamp
> to counter.
>
> Signed-off-by: Leo Yan
> ---
> tools/perf/util/Build| 1 +
>
Hi Leo
On 2020/8/7 15:16, Leo Yan wrote:
> The Arm arch timer can be used to calculate timestamp, the basic idea is
> the arch timer's counter value can be recorded in the hardware tracing
> data, e.g. the arch timer's counter value can be used for Arm CoreSight
> (not now but might be
Ping...
On 2020/7/24 16:32, Leo Yan wrote:
> Hi Wei,
>
> On Fri, Jul 24, 2020 at 03:26:28PM +0800, Wei Li wrote:
>> In arm_spe_read_record(), when we are processing an events packet,
>> 'decoder->packet.index' is the length of payload, which has been
>> transformed in payloadlen(). So correct
On 2020/7/30 16:14, Leo Yan wrote:
> Hi Suzuki,
>
> On Wed, Jul 29, 2020 at 10:12:50AM +0100, Suzuki Kuruppassery Poulose wrote:
>> On 07/24/2020 10:16 AM, Wei Li wrote:
>>> Armv8.3 extends the SPE by adding:
>>> - Alignment field in the Events packet, and filtering on this event
>>>using
Hi Leo,
On 2020/7/29 15:28, Leo Yan wrote:
> On Wed, Jul 29, 2020 at 03:21:20PM +0800, liwei (GF) wrote:
>
> [...]
>
>>>> @@ -354,8 +372,38 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt
>>>> *packet, char *buf,
>>>>}
>>&
Hi Leo,
On 2020/7/29 14:29, Leo Yan wrote:
> On Fri, Jul 24, 2020 at 05:16:05PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension (SVE).
>>
>> The
Hi Leo,
On 2020/7/28 20:27, Leo Yan wrote:
> Hi Wei,
>
> On Fri, Jul 24, 2020 at 05:16:04PM +0800, Wei Li wrote:
>> Armv8.3 extends the SPE by adding:
>> - Alignment field in the Events packet, and filtering on this event
>> using PMSEVFR_EL1.
>> - Support for the Scalable Vector Extension
Hi Yingliang,
On 2020/7/21 22:38, Yang Yingliang wrote:
(SNIP)
>
> SERIAL_PORT_DFNS is not defined on each arch, if it's not defined,
> serial8250_set_defaults() won't be called in serial8250_isa_init_ports(),
> so the p->serial_in pointer won't be initialized, and it leads a
> null-ptr-deref.
Hi Doug,
On 2020/6/30 5:20, Doug Anderson wrote:
> Wei,
>
> On Sat, May 16, 2020 at 1:20 AM liwei (GF) wrote:
>>
>> Hi Douglas,
>>
>> On 2020/5/14 8:34, Doug Anderson wrote:
>>> Hi,
>>>
>>> On Sat, May 9, 2020 at 6:49 AM Wei Li wrote:
Hi Mathieu,
On 2020/7/3 7:03, Mathieu Poirier wrote:
> Hi Li,
>
> On Tue, Jun 23, 2020 at 08:31:41PM +0800, Wei Li wrote:
>> When recording with cache-misses and arm_spe_x event, i found that
>> it will just fail without showing any error info if i put cache-misses
>> after arm_spe_x event.
>>
Ping...
On 2020/6/12 23:19, Namhyung Kim wrote:
> Hello,
>
> On Fri, Jun 12, 2020 at 6:58 PM Wei Li wrote:
>>
>> The segmentation fault can be reproduced as following steps:
>> 1) Executing perf report in tui.
>> 2) Typing '/x' to filter the symbol to get nothing matched.
>> 3) Pressing
Hi Daniel,
On 2020/5/19 19:40, Daniel Thompson wrote:
> On Sat, May 16, 2020 at 05:26:06PM +0800, Wei Li wrote:
>> 'KDBFLAGS' is an internal variable of kdb, it is combined by 'KDBDEBUG'
>> and state flags. But the user can define an environment variable named
>> 'KDBFLAGS' too, so let's make it
Hi Douglas,
On 2020/5/14 8:21, Doug Anderson wrote:
(SNIP)
>> +/*
>> + * Interrupts need to be disabled before single-step mode is set, and not
>> + * reenabled until after single-step mode ends.
>> + * Without disabling interrupt on local CPU, there is a chance of
>> + * interrupt occurrence in
Hi Douglas,
On 2020/5/14 8:34, Doug Anderson wrote:
> Hi,
>
> On Sat, May 9, 2020 at 6:49 AM Wei Li wrote:
>>
>> This patch set is to fix several issues of single-step debugging
>> in kgdb/kdb on arm64.
>>
>> It seems that these issues have been shelved a very long time,
>> but i still hope to
Hi Douglas,
On 2020/5/14 8:23, Doug Anderson wrote:
(SNIP)
>> diff --git a/arch/arm64/kernel/kgdb.c b/arch/arm64/kernel/kgdb.c
>> index 3910ac06c261..093ad9d2e5e6 100644
>> --- a/arch/arm64/kernel/kgdb.c
>> +++ b/arch/arm64/kernel/kgdb.c
>> @@ -230,7 +230,8 @@ int kgdb_arch_handle_exception(int
Hi Douglas,
On 2020/5/14 7:41, Doug Anderson wrote:
>> - }
>> + } else if (strcmp(argv[1], "KDBFLAGS") == 0)
>> + return KDB_NOPERM;
>
> One slight nit is that my personal preference is that if one half of
> an "if/else" needs braces then both halves should have
Hi Marc,
On 2019/10/2 17:06, Marc Zyngier wrote:
> The GICv3 architecture specification is incredibly misleading when it
> comes to PMR and the requirement for a DSB. It turns out that this DSB
> is only required if the CPU interface sends an Upstream Control
> message to the redistributor in
Hi Arnaldo,
I found this issue has not been fixed in mainline now, please take a glance at
this.
On 2019/5/23 10:50, Namhyung Kim wrote:
> On Wed, May 22, 2019 at 08:08:23AM -0300, Arnaldo Carvalho de Melo wrote:
>> Em Wed, May 22, 2019 at 03:56:10PM +0900, Namhyung Kim escreveu:
>>> On Wed, May
Hi Alex,
On 2019/3/29 23:20, Alex Kogan wrote:
> In CNA, spinning threads are organized in two queues, a main queue for
> threads running on the same node as the current lock holder, and a
> secondary queue for threads running on other nodes. At the unlock time,
> the lock holder scans the main
Hi Jiriļ¼
Thanks for your reply.
On 2019/5/7 16:51, Jiri Olsa wrote:
> On Fri, May 03, 2019 at 10:35:55AM +0800, Wei Li wrote:
>> After thread is added to machine->threads[i].dead in
>> __machine__remove_thread, the machine->threads[i].dead is freed
>> when calling free(session) in
Hi Julien,
On 2019/4/2 22:00, Julien Thierry wrote:
I meet this issue by coincidence before too.
> I finally found out what happens.
>
> When using interrupt priority masking, at the begining of
> gic_handle_irq(), we are in this awkward state where we still have the I
> bit set and PMR
Hi Arnaldo,
Please shoot a glance at this modification, i think this issue is influential.
On 2019/2/28 19:28, Jiri Olsa Wrote:
> On Thu, Feb 28, 2019 at 05:20:03PM +0800, Wei Li wrote:
>> Since commit 1fb87b8e9599 ("perf machine: Don't search for active kernel
>> start in
Hi peter,
The syzkaller reported a task hung issue, and it was on a qemu x86_64 machine
with kernel 4.19.27.
I analysed and found that, the gctx got in __perf_event_ctx_lock_double and ctx
are just equal.It is
caused by race between two concurrent sys_perf_event_open() calls where both
try and
> On 26/01/2019 10:19, liwei (GF) wrote:
>>
>>
>> On 2019/1/21 23:33, Julien Thierry wrote:
>>> Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers
>>> when setting up interrupt line as NMI.
>>>
>>> Only SPIs and PPIs are
On 2019/1/21 23:33, Julien Thierry wrote:
> Implement NMI callbacks for GICv3 irqchip. Install NMI safe handlers
> when setting up interrupt line as NMI.
>
> Only SPIs and PPIs are allowed to be set up as NMI.
>
> Signed-off-by: Julien Thierry
> Cc: Thomas Gleixner
> Cc: Jason Cooper
> Cc:
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