On Fri, Oct 11, 2024 at 10:12:09AM +0300, Dmitry Baryshkov wrote:
> On Fri, 11 Oct 2024 at 10:09, Shiraz Hashim wrote:
> >
> > On Fri, Oct 11, 2024 at 09:23:05AM +0300, Dmitry Baryshkov wrote:
> > > On Fri, Oct 11, 2024 at 10:35:18AM GMT, Shiraz Hashim wrote:
> > >
On Fri, Oct 11, 2024 at 09:09:08AM +0200, neil.armstr...@linaro.org wrote:
> On 11/10/2024 07:05, Shiraz Hashim wrote:
> > On Thu, Oct 10, 2024 at 08:57:56AM +0200, neil.armstr...@linaro.org wrote:
> > > On 08/10/2024 08:21, Mukesh Ojha wrote:
> > > > On Mon, Oc
On Fri, Oct 11, 2024 at 09:23:05AM +0300, Dmitry Baryshkov wrote:
> On Fri, Oct 11, 2024 at 10:35:18AM GMT, Shiraz Hashim wrote:
> > On Thu, Oct 10, 2024 at 08:57:56AM +0200, neil.armstr...@linaro.org wrote:
> > > On 08/10/2024 08:21, Mukesh Ojha wrote:
> > > > On M
On Thu, Oct 10, 2024 at 08:57:56AM +0200, neil.armstr...@linaro.org wrote:
> On 08/10/2024 08:21, Mukesh Ojha wrote:
> > On Mon, Oct 07, 2024 at 08:22:39PM +0530, Mukesh Ojha wrote:
> > > On Mon, Oct 07, 2024 at 10:05:08AM +0200, neil.armstr...@linaro.org wrote:
> > > > On 04/10/2024 23:23, Mukesh
On Thu, Oct 10, 2024 at 09:15:59AM +0200, Krzysztof Kozlowski wrote:
> On 09/10/2024 16:04, Shiraz Hashim wrote:
> > On Mon, Oct 07, 2024 at 06:25:01PM +0200, Dmitry Baryshkov wrote:
> >> On Mon, 7 Oct 2024 at 17:35, Mukesh Ojha wrote:
> >>>
> >>> On Sun
On Mon, Oct 07, 2024 at 06:25:01PM +0200, Dmitry Baryshkov wrote:
> On Mon, 7 Oct 2024 at 17:35, Mukesh Ojha wrote:
> >
> > On Sun, Oct 06, 2024 at 10:38:01PM +0300, Dmitry Baryshkov wrote:
> > > On Sat, Oct 05, 2024 at 02:53:54AM GMT, Mukesh Ojha wrote:
>
On Sun, Oct 06, 2024 at 10:34:19PM +0300, Dmitry Baryshkov wrote:
> On Sat, Oct 05, 2024 at 02:53:53AM GMT, Mukesh Ojha wrote:
> > Qualcomm is looking to enable remote processors on the SA8775p SoC
> > running KVM Linux host and is currently trying to figure out an
> > upstream-compatible solution
leads to
kernel crash, as subsequent code assumes that requested
memory is available.
Fail cma allocation in case the request breaches the
corresponding cma region size.
Signed-off-by: Shiraz Hashim
---
mm/cma.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/mm/cma.c b/mm/cma.c
index 384c2cb
ork_on(CPU0)
quiet_vmstat
cancel_delayed_work
cpumask_test_and_set_cpu (0->1)
cpumask_clear_cpu(CPU0) (1->0)
--
regards
Shiraz Hashim
On Wed, Jan 20, 2016 at 8:42 PM, Christoph Lameter wrote:
> On Wed, 20 Jan 2016, Shiraz Hashim wrote:
>
>> The patch makes vmstat_shepherd deferable which if is quiesed
>> would not schedule vmstat update on other cpus. Wouldn't this
>> aggravate the problem of vm
index.
Signed-off-by: Shiraz Hashim
---
The fix is revised, based upon the suggestion here at
http://www.spinics.net/lists/linux-mm/msg83058.html
mm/pagewalk.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/mm/pagewalk.c b/mm/pagewalk.c
index ad83195..b264bda 100644
On Wed, Jan 14, 2015 at 01:08:40AM +, Naoya Horiguchi wrote:
> On Tue, Jan 13, 2015 at 05:57:04PM +0530, Shiraz Hashim wrote:
> > pagemap_read scans through the virtual address space of a
> > task till it prepares 'count' pagemaps or it reaches end
> > of task.
&
in turn making
pagemap_read to scan through task end, even crossing beyond
'count', landing into a different vma region. This leads to
wrong presentation of mappings for that vma.
Fix this by limiting end_vaddr to the end of the virtual
address region being scanned.
Signed-off-by: Sh
pear_pwm_chip(struct pwm_chip *chip)
> @@ -200,7 +198,6 @@ static int spear_pwm_probe(struct platform_device *pdev)
> if (IS_ERR(pc->clk))
> return PTR_ERR(pc->clk);
>
> - pc->dev = &pdev->dev;
> platform_set_drvdata(pdev, pc);
>
&
On Sat, Mar 30, 2013 at 05:55:41PM +0800, Viresh Kumar wrote:
> On 30 March 2013 11:07, Axel Lin wrote:
> > The logic to check return value of clk_enable() is reversed, thus
> > when clk_enable() passes PWMCR_PWM_ENABLE bit is not set. Fix it.
> >
> > Signed-off-by: Axel Lin
> > ---
> > drivers/
Hi Nicolas,
On Fri, Feb 08, 2013 at 12:49:22PM -0500, Nicolas Pitre wrote:
> On Fri, 8 Feb 2013, Viresh Kumar wrote:
> >
> > By mistake you have added an ST internal list in cc, fixed it now.
> >
> > Subject should be:
> >
> > ARM: SPEAr13xx: Enable 2G/2G Memory split in defconfig
> >
> > On 8
On Sat, Dec 1, 2012 at 10:05 PM, Linus Walleij wrote:
> On Mon, Nov 26, 2012 at 12:32 PM, Shiraz Hashim wrote:
>> On Mon, Nov 26, 2012 at 11:28:23AM +, Lee Jones wrote:
>>>
>>> Doesn't pinctrl normally handle this kind of stuff?
>>
>> Yes, but I t
On Mon, Nov 26, 2012 at 11:28:23AM +, Lee Jones wrote:
> On Fri, 23 Nov 2012, Shiraz Hashim wrote:
>
> > On Fri, Nov 23, 2012 at 12:14:13PM +, Lee Jones wrote:
> > > > >> + if (np)
> > > > >> +
On Fri, Nov 23, 2012 at 12:14:13PM +, Lee Jones wrote:
> > >> + if (np)
> > >> + of_property_read_u32(np, "st,norequest-mask",
> > >> + &pdata->norequest_mask);
> > >
> > > Can you explain to me what this does?
> >
> > You mea
On Thu, Nov 22, 2012 at 10:31:48PM +0530, Viresh Kumar wrote:
> On 22 November 2012 21:16, Lee Jones wrote:
> > The STMPE GPIO controller can't be used by Device Tree yet in
> > any case, because it doesn't have an IRQ domain. This is
> > compulsory, or it won't work. Have you tried to test this
>
Hi Mike,
On Tue, Nov 13, 2012 at 2:52 AM, Mike Turquette wrote:
> Quoting Shiraz Hashim (2012-11-06 22:36:10)
>> On Wed, Nov 7, 2012 at 11:42 AM, Shiraz Hashim
>> wrote:
>> > Hi Mike, Rob,
>> >
>> > Devices in a SoC can have multiple possible cloc
Hi Catalin,
On Mon, Nov 12, 2012 at 10:56:41AM +, Will Deacon wrote:
> On Mon, Nov 12, 2012 at 06:45:47AM +0000, Shiraz Hashim wrote:
> > On Fri, Nov 09, 2012 at 09:54:01AM +, Will Deacon wrote:
> > > On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote:
>
On Fri, Nov 09, 2012 at 09:54:01AM +, Will Deacon wrote:
> On Fri, Nov 09, 2012 at 04:01:52AM +0000, Shiraz Hashim wrote:
> > From: Catalin Marinas
> >
> > Clearing bit 22 in the PL310 Auxiliary Control register (shared
> > attribute override enable) has the
/mcu/product/251211.jsp
Cc: Thierry Reding
Signed-off-by: Shiraz Hashim
Signed-off-by: Viresh Kumar
Reviewed-by: Vipin Kumar
Acked-by: Viresh Kumar
---
Changes:-
V4 --> V5:
* replace tab by space in structure element declaration
* restructure probe to register pwm_chip at end when clk
On Wed, Oct 24, 2012 at 07:51:37AM +0200, Thierry Reding wrote:
> On Mon, Oct 22, 2012 at 04:36:41PM +0530, Shiraz Hashim wrote:
> [...]
> > +struct spear_pwm_chip {
> > + void __iomem *mmio_base;
> > + struct clk *clk;
> > + struct pwm_chip chip;
>
> My
/mcu/product/251211.jsp
Cc: Thierry Reding
Signed-off-by: Shiraz Hashim
Signed-off-by: Viresh Kumar
Reviewed-by: Vipin Kumar
---
Changes:-
V3 --> V4:
* simplify remove
* maintain alphabetical order in Makefile
* donot check for device node in probe
* move few assignment lines in pr
Hi Viresh,
On Mon, Oct 22, 2012 at 09:39:21AM +0530, viresh kumar wrote:
> Every time you read a code, you figure out new things about it.
> Sorry for these comments Now :(
No problem, it is important to fix now than catch them later.
> On Mon, Oct 22, 2012 at 9:21 AM, Shiraz Hash
/mcu/product/251211.jsp
Cc: Thierry Reding
Signed-off-by: Shiraz Hashim
Signed-off-by: Viresh Kumar
Reviewed-by: Vipin Kumar
---
Changes:-
V2 --> V3:
* remove "disabled" line from pwm dt binding documentation
* remove un-necessary check on pwm chip (for NULL) in remove.
Hi Viresh,
On Fri, Oct 19, 2012 at 7:14 PM, Viresh Kumar wrote:
> On 19 October 2012 15:45, Shiraz Hashim wrote:
>> diff --git a/Documentation/devicetree/bindings/pwm/spear-pwm.txt
>> b/Documentation/devicetree/bindings/pwm/spear-pwm.txt
>> +
/mcu/product/251211.jsp
Cc: Thierry Reding
Signed-off-by: Shiraz Hashim
Signed-off-by: Viresh Kumar
Reviewed-by: Vipin Kumar
---
Changes V1 --> V2:
* make proper reference to pwm and pwm chip
* take care to capitalize PWM at appropriate places
* fix compatible string to the SoC where
On Fri, Oct 19, 2012 at 11:29:43AM +0530, Shiraz HASHIM wrote:
> On Thu, Oct 18, 2012 at 11:11:06PM +0530, viresh kumar wrote:
> > On Thu, Oct 18, 2012 at 4:58 PM, Shiraz Hashim wrote:
> > > + pc->mmio_base = devm_request_and_ioremap(&pdev->dev, r);
>
Hi Viresh,
On Fri, Oct 19, 2012 at 12:23:08PM +0530, viresh kumar wrote:
> On Fri, Oct 19, 2012 at 11:29 AM, Shiraz Hashim wrote:
> > On Thu, Oct 18, 2012 at 11:11:06PM +0530, viresh kumar wrote:
> >> On Thu, Oct 18, 2012 at 4:58 PM, Shiraz Hashim
> >> wrote:
>
Hi Viresh,
On Thu, Oct 18, 2012 at 11:11:06PM +0530, viresh kumar wrote:
> On Thu, Oct 18, 2012 at 4:58 PM, Shiraz Hashim wrote:
> > diff --git a/Documentation/devicetree/bindings/pwm/st-spear-pwm.txt
> > b/Documentation/devicetree/bindings/pwm/st-spear-pwm.txt
> >
Hi Thierry,
Thanks for the quick review.
On Thu, Oct 18, 2012 at 02:08:20PM +0200, Thierry Reding wrote:
> On Thu, Oct 18, 2012 at 04:58:32PM +0530, Shiraz Hashim wrote:
> > Add support for pwm devices present on SPEAr platforms. These pwm
> > devices support 4 channel output wi
/internet/mcu/product/251211.jsp
Cc: Thierry Reding
Signed-off-by: Shiraz Hashim
Signed-off-by: Viresh Kumar
Reviewed-by: Vipin Kumar
---
.../devicetree/bindings/pwm/st-spear-pwm.txt | 19 ++
drivers/pwm/Kconfig| 10 +
drivers/pwm/Makefile
Hi Linus,
On Sun, Sep 2, 2012 at 12:48 PM, Linus Walleij wrote:
> On Sat, Sep 1, 2012 at 1:14 PM, shiraz hashim
> wrote:
>> Hi Roland,
>>
>> On Wed, Aug 22, 2012 at 7:19 PM, Roland Stigge wrote:
>>> @@ -2016,6 +2030,8 @@ pl022_probe(struct amba_device *adev,
selects to allocated memory beyond the main struct */
> + pl022->chipselects = (int *) pl022 + sizeof(struct pl022);
This is going beyond memory allocated for chipselects
as it adds 4 * sizeof(struct pl022) bytes to pl022.
pl022->chipselects = (int *) &pl022[1];
can be musch
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