privatization and encryption for it to be SNP agnostic
8. Assert for only positive tests using vm_ioctl()
9. Dropped tested-by tags
Tested-by: Srikanth Aithal
In summary - based on comments from Sean, I have primarily reduced the
scope of this patch series to focus on breaking down the SNP smoke
oundation.org; cor...@lwn.net; leonard.cres...@nxp.com;
> palmerdabb...@google.com; paul.walms...@sifive.com; peng@nxp.com;
> robh...@kernel.org; shawn...@kernel.org; jassisinghb...@gmail.com
> Cc: linux-kernel@vger.kernel.org; Thokala, Srikanth
> ; linux-...@vger.kernel.org
> S
Hi Greg,
> -Original Message-
> From: Greg KH
> Sent: Sunday, January 24, 2021 5:27 PM
> To: Thokala, Srikanth
> Cc: mgr...@linux.intel.com; markgr...@kernel.org; a...@arndb.de;
> b...@suse.de; damien.lem...@wdc.com; dragan.cve...@xilinx.com;
> cor...@lwn.net; le
et;
> leonard.cres...@nxp.com; palmerdabb...@google.com;
> paul.walms...@sifive.com; peng@nxp.com; robh...@kernel.org;
> shawn...@kernel.org; jassisinghb...@gmail.com; linux-
> ker...@vger.kernel.org; Thokala, Srikanth ;
> Derek Kiernan
> Subject: Re: [PATCH v2 09/34] misc: xlink
et;
> leonard.cres...@nxp.com; palmerdabb...@google.com;
> paul.walms...@sifive.com; peng@nxp.com; robh...@kernel.org;
> shawn...@kernel.org; jassisinghb...@gmail.com; linux-
> ker...@vger.kernel.org; Thokala, Srikanth
> Subject: Re: [PATCH v2 15/34] misc: xlink-pcie: Add XLink
Hi Greg,
> -Original Message-
> From: Greg Kroah-Hartman
> Sent: Tuesday, December 1, 2020 3:48 PM
> To: mgr...@linux.intel.com
> Cc: linux-kernel@vger.kernel.org; markgr...@kernel.org; Gretzinger, Adam R
> ; Thokala, Srikanth
> ; Derek Kiernan ;
> Draga
.@nxp.com; palmerdabb...@google.com;
> paul.walms...@sifive.com; peng@nxp.com; robh...@kernel.org;
> shawn...@kernel.org; linux-kernel@vger.kernel.org; Thokala, Srikanth
>
> Subject: Re: [PATCH 09/22] misc: xlink-pcie: lh: Add core communication
> logic
>
> On Tue, Dec 01, 2020 a
Jan Kiszka
Cc: Cedric Hombourger
Signed-off-by: Srikanth Krishnakar
---
Suggested for linux-stable v4.14.x and above.
Depends on ad0d315b4d4e ("platform/x86: pmc_atom: Add Siemens SIMATIC IPC227E
to critclk_systems DMI table")
drivers/platform/x86/pmc_atom.c | 7 +++
1 file c
identical names.
Tested on SIMATIC IPC227E and IPC277E.
Fixes: 648e921888ad ("clk: x86: Stop marking clocks as CLK_IS_CRITICAL")
CC: Jan Kiszka
CC: Cedric Hombourger
Signed-off-by: Srikanth Krishnakar
---
drivers/platform/x86/pmc_atom.c | 9 -
1 file changed, 8 insertions(+),
Hello,
On power9 host, performing memory hotunplug from ppc64le guest results
in kernel oops.
Kernel used : https://github.com/torvalds/linux/tree/v5.1 built using
ppc64le_defconfig for host and ppc64le_guest_defconfig for guest.
Recreation steps:
1. Boot a guest with below mem configurati
ned-off-by: Srikanth Boddepalli
---
drivers/xen/xlate_mmu.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/xen/xlate_mmu.c b/drivers/xen/xlate_mmu.c
index 23f1387..e7df65d 100644
--- a/drivers/xen/xlate_mmu.c
+++ b/drivers/xen/xlate_mmu.c
@@ -36,6 +36,7 @@
#include
#include
> If the pin descriptor requested for the physical pin fails then the
> descriptor is dereferenced without checking for its validity which
> may lead to crash, hence added preventive code to check for NULL
> and accordingly dereference.
> Signed-off-by: Srikanth K H
> ---
If the pin descriptor requested for the physical pin fails then the
descriptor is dereferenced without checking for its validity which
may lead to crash, hence added preventive code to check for NULL
and accordingly dereference.
Signed-off-by: Srikanth K H
---
drivers/pinctrl/pinconf.c | 5
> It is fine to crash because /proc is not modular.
Dear Alexey, this was theoretical solution. If you feel this should crash
instead if the call fail's then ignore the patch.
Regards,
Srikanth
ng one here.
Regards,
Srikanth
If the make directory for "sys" interface fail's then its
dereferenced without even checking for its validity which
will lead to crash, hence added preventive code to check
for NULL and accordingly dereference.
Signed-off-by: Srikanth K H
---
fs/proc/proc_sysctl.c | 2 ++
1
ou said this changes will catch buggy code in caller
side.
Thank you for your respose.
Thanks,
Srikanth
ence kernel
panic occur. So as preventive measure while the creating
the sound timer object is created the card information
availability is checked for the mentioned entries and
returned error if its NULL.
Signed-off-by: Srikanth K H
---
sound/core/timer.c | 11 +++
1 file changed, 7 inser
>>
>> Signed-off-by: Srikanth K H
>What does this fix, and above all, why is this needed?
Hi,
When the sound driver creates the timer without sound card object, then while
reading the sound info entry the timer object’s card information is
dereferenced without checking f
Signed-off-by: Srikanth K H
---
sound/core/timer.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/sound/core/timer.c b/sound/core/timer.c
index b6f076bb..c7be4f1 100644
--- a/sound/core/timer.c
+++ b/sound/core/timer.c
@@ -1192,10 +1192,12 @@ static void
This patchset adds the firmware for CNN55XX cryto driver,
supports Symmetric crypto operations.
The version of the firmware is v07.
Signed-off-by: Srikanth Jampala
---
WHENCE | 9 +
cavium/cnn55xx_se.fw | Bin 0 -> 27698 bytes
2 files changed, 9 insertions(+)
cre
This patchset adds firmware for CNN55XX crypto driver, which supports
the Symmetric crypto operations.
Changes from v1 to v2:
- Moved firmware to "cavium" subdirectory as suggested by
Kyle McMartin.
Srikanth Jampala (1):
cavium: Add firmware for CNN55XX crypto driver
Moved the firmware to "cavium" subdirectory as suggested by
Kyle McMartin.
Signed-off-by: Srikanth Jampala
---
drivers/crypto/cavium/nitrox/nitrox_main.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/crypto/cavium/nitrox/nitrox_main.c
b/drivers/cry
Sure kyle, I will work on this.
Thanks.
On Friday 23 June 2017 12:39 AM, Kyle McMartin wrote:
> On Fri, Jun 16, 2017 at 07:52:26PM +0530, Srikanth Jampala wrote:
>> This patchset adds the firmware for CNN55XX cryto driver,
>> supports Symmetric crypto operations.
>>
This patchset adds the firmware for CNN55XX cryto driver,
supports Symmetric crypto operations.
The version of the firmware is v07.
Signed-off-by: Srikanth Jampala
---
WHENCE| 9 +
cnn55xx_se.fw | Bin 0 -> 27698 bytes
2 files changed, 9 insertions(+)
create mode 100
CNN55XX driver is accepted and needs firmware to functional.
This patchset adds CNN55XX firmware v07 supports
symmetric crypto operations.
Srikanth Jampala (1):
cavium: Add firmware for CNN55XX crypto driver.
WHENCE| 9 +
cnn55xx_se.fw | Bin 0 -> 27698 bytes
2 files chan
Add debugfs support in CNN55XX Physical Function driver.
Provides hardware counters and firmware information.
Signed-off-by: Srikanth Jampala
---
drivers/crypto/cavium/nitrox/nitrox_csr.h | 4 +
drivers/crypto/cavium/nitrox/nitrox_dev.h | 4 +
drivers/crypto/cavium/nitrox/nitrox_main.c
Add Physical Function driver support for CNN55XX crypto adapters.
CNN55XX adapters belongs to Cavium NITROX family series,
which accelerate both Symmetric and Asymmetric crypto workloads.
These adapters have crypto engines that need firmware
to become operational.
Signed-off-by: Srikanth Jampala
.
- Clear the context information while releasing.
- Cleanup in request processing, avoids unnecessary copies.
- Use refcount_t type for reference counters.
- Dependencies updated in Kconfig.
Srikanth Jampala (3):
crypto: cavium - Add support for CNN55XX adapters.
crypto: cavium - Add debugfs support
Register the Symmetric crypto algorithms supported by
CNN55XX driver with crypto subsystem.
The following Symmetric crypto algorithms are supported,
- aes with cbc, ecb, cfb, xts, ctr and cts modes
- des3_ede with cbc and ecb modes
Signed-off-by: Srikanth Jampala
---
drivers/crypto/cavium
Hi Stephan,
On Thursday 11 May 2017 05:52 PM, Stephan Müller wrote:
> Am Donnerstag, 11. Mai 2017, 14:18:34 CEST schrieb srikanth jampala:
>
> Hi srikanth,
>
>> Hi Stephan,
>>
>> On Wednesday 10 May 2017 07:26 PM, Stephan Müller wrote:
>>> Am Mittwo
Hi Stephan,
On Wednesday 10 May 2017 07:26 PM, Stephan Müller wrote:
> Am Mittwoch, 10. Mai 2017, 15:06:40 CEST schrieb Srikanth Jampala:
>
> Hi Srikanth,
>
> In general: you are using the ablkcipher API. I think it is on its way out
> and
> being replaced with skcipher
Register the Symmetric crypto algorithms supported by
CNN55XX driver with crypto subsystem.
The following Symmetric crypto algorithms are supported,
- aes with cbc, ecb, cfb, xts, ctr and cts modes
- des3_ede with cbc and ecb modes
Signed-off-by: Srikanth Jampala
---
drivers/crypto/cavium
Add Physical Function driver support for CNN55XX crypto adapters.
CNN55XX adapters belongs to Cavium NITROX family series,
which accelerate both Symmetric and Asymmetric crypto workloads.
These adapters have crypto engines that need firmware
to become operational.
Signed-off-by: Srikanth Jampala
Add debugfs support in CNN55XX Physical Function driver.
Provides hardware counters and firmware information.
Signed-off-by: Srikanth Jampala
---
drivers/crypto/cavium/nitrox/nitrox_csr.h | 5 ++
drivers/crypto/cavium/nitrox/nitrox_dev.h | 3 +
drivers/crypto/cavium/nitrox/nitrox_main.c
ernel
cryptographic offload operations.
Please provide the feeback.
Srikanth Jampala (3):
crypto: cavium - Add support for CNN55XX adapters.
crypto: cavium - Add debugfs support in CNN55XX driver
crypto: cavium - Register the CNN55XX supported crypto algorithms.
dr
Hi,
Kindly review the patch.
Thanks
Srikanth
On Tue, Nov 18, 2014 at 10:09 AM, Srikanth Thokala
wrote:
> In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
> match the sequence of events described below it. To match the
> sequence of events, t
In the first example, the loads into 'x' and 'y' on CPU 2 doesn't
match the sequence of events described below it. To match the
sequence of events, the values of 'A' and 'B' should be loaded
into 'x' and 'y' respectively.
Signed
Hi,
On Wed, Nov 12, 2014 at 12:26 PM, Srikanth Thokala
wrote:
> Hi,
>
> On Wed, Nov 12, 2014 at 12:47 AM, wrote:
>> From: Suravee Suthikulpanit
>>
>> This patch introduces a new DT binding, msi-parent, which can
>> be used to specify MSI-parent phandle for
> +static int gen_pci_set_msi_parent(struct pci_bus *bus)
> +{
> + struct gen_pci *pci = bus_to_gen_pci(bus);
> +
> + bus->msi = pci->mchip;
> +
> + return PCIBIOS_SUCCESSFUL;
> +}
> +
> static struct pci_ops gen_pci_ops = {
>
unsubscribe
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majord...@vger.kernel.org
More majordomo info at http://vger.kernel.org/majordomo-info.html
Please read the FAQ at http://www.tux.org/lkml/
return rc;
> }
> - rc = once_over (); /* This is to align ranges (so no -1) */
> - if (rc)
> - return rc;
> - return 0;
> + return once_over();
I think we need to retain the comment?
- Srikanth
> }
>
>
> /
Hi Mark,
Thanks for reviewing patch.
I should have made a note that the binding patch is applied. I will
make a note of this and add to next versions.
Thanks
Srikanth
On Wed, Oct 15, 2014 at 6:15 PM, Mark Rutland wrote:
> Hi,
>
> On Wed, Oct 15, 2014 at 01:00:36PM +0100, Srikant
: Srikanth Thokala
---
Changes in v4:
- Add direction field to VDMA descriptor structure and removed from
channel structure to avoid duplication.
- Check for DMA idle condition before changing the configuration.
- Residue is being calculated in complete_descriptor() and is reported
to slave driver
Hi Vinod,
On Tue, Sep 9, 2014 at 9:27 PM, Vinod Koul wrote:
> On Tue, Sep 09, 2014 at 12:52:16AM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
>> > On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth
Hi Vinod,
On Thu, Sep 4, 2014 at 12:06 PM, Vinod Koul wrote:
> On Wed, Sep 03, 2014 at 12:17:43PM +0530, Srikanth Thokala wrote:
>> Hi Vinod,
>>
>> Apologies for the delay.
>>
>> On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
>> > On Mon, Jul 28,
On Wed, Sep 3, 2014 at 11:35 PM, Bjorn Helgaas wrote:
> On Wed, Aug 20, 2014 at 09:56:02PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> Acked-by: Arnd Bergmann
>
> App
Hi Bjorn,
I fixed the mentioned issues with build-bot in v7. Could you please
take this patch?
Thanks
Srikanth
On Wed, Aug 20, 2014 at 9:56 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> Acked-by: A
Hi Vinod,
Apologies for the delay.
On Tue, Aug 19, 2014 at 10:33 PM, Vinod Koul wrote:
> On Mon, Jul 28, 2014 at 05:47:49PM +0530, Srikanth Thokala wrote:
>> +struct xilinx_dma_chan {
>> + struct xilinx_dma_device *xdev;
>> + u32 ctrl_offset;
>> + spinl
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
Changes in v7:
- Removed errors reported from build-bot. The errors are
mainly due to same CONFIG_PCI_XILINX flag being used for
Zynq and Microblaze platforms. So
Hi Bjorn,
On Tue, Aug 19, 2014 at 12:19 AM, Bjorn Helgaas wrote:
> On Mon, Aug 18, 2014 at 02:47:23PM +0530, Srikanth Thokala wrote:
>> Hi Michal,
>>
>> On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
>> > Hi Bjorn,
>> >
>> > On 07/30/2014
Hi Varka Bhadram,
On Tue, Aug 5, 2014 at 5:29 PM, Varka Bhadram wrote:
> On 08/05/2014 05:09 PM, Srikanth Thokala wrote:
>>
>> Device-tree binding documentation of Xilinx Central DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v2:
&g
Hi Michal,
On Tue, Aug 12, 2014 at 3:07 PM, Michal Simek wrote:
> Hi Bjorn,
>
> On 07/30/2014 01:24 PM, Srikanth Thokala wrote:
>> Hi Arnd,
>>
>> On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
>>> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrot
Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Rebased on 3.16-rc7.
---
drivers/dma/Kconfig | 12 +
drivers/dma/xilinx/Makefile |1 +
drivers/dma/xilinx/xilinx_cdma.c | 998 ++
include/linux/amba/xilinx_dma.h
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
---
.../devicetree/bindings/dma/xilinx/xi
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
Acked-by: Arnd Bergmann
---
NOTE: The AXI PCIe IP doesn't support I/O space, so this
driver has no support for I/O space.
Changes in v6:
- Added Ack from Arnd. Thanks Arnd.
- Rebased on 3.1
Hi,
Kindly review this patch and please provide your inputs.
Thanks
Srikanth
On Mon, Jul 28, 2014 at 5:47 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwidth direct memo
Hi Arnd,
On Mon, Jul 28, 2014 at 6:32 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 18:04:34 Srikanth Thokala wrote:
>> Hi Arnd and Rob,
>>
>> I discussed with Bjorn and we believe this patch is in good shape to
>> apply. And Bjorn requires ACKs to apply this pa
On Mon, Jul 28, 2014 at 5:58 PM, Arnd Bergmann wrote:
> On Monday 28 July 2014 17:47:48 Srikanth Thokala wrote:
>> Device-tree binding documentation of Xilinx DMA Engine
>>
>> Signed-off-by: Srikanth Thokala
>
> Looks ok to me,
>
> Acked-by: Arnd Bergmann
Hi Arnd and Rob,
I discussed with Bjorn and we believe this patch is in good shape to
apply. And Bjorn requires ACKs to apply this patch. So, could you
guys please review this patch and provided your ACKs to this patch.
Thanks
Srikanth
On Wed, Jul 23, 2014 at 9:33 PM, Srikanth Thokala wrote
: Srikanth Thokala
---
Changes in v3:
- Rebased on 3.16-rc7
Changes in v2:
- Simplified the logic to set SOP and APP words in prep_slave_sg().
- Corrected function description comments to match the return type.
- Fixed some minor comments as suggested by Andy, Thanks.
---
drivers/dma/Kconfig
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Change property 'xlnx,data-width' to 'xlnx,datawidth' in the description
to match the implementation.
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xi
Hi Andreas,
> -Original Message-
> From: Michal Simek [mailto:michal.si...@xilinx.com]
> Sent: Friday, July 25, 2014 3:10 PM
> To: Andreas Färber; mon...@monstr.eu; Srikanth Thokala
> Cc: Vinod Koul; Michal Simek; Andreas Olofsson; Matteo Vit; Sean Rickerd;
> devicet.
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v5:
- Removed unnecessary checking of port structure.
- Changed the return type of verify_config from int to bool.
- Renamed following functions,
xilinx_pcie_is_link_up
Hi Bjorn,
On Wed, Jul 16, 2014 at 11:08 PM, Bjorn Helgaas wrote:
> On Thu, Jul 03, 2014 at 09:57:34AM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v4:
- Regarding the comments to separate ECAM functionality,
I have sent a separate patch and it is decided to implement
it later. The patch is here,
https://lkml.org/lkml/2014/5/18/54
> -Original Message-
> From: Arnd Bergmann [mailto:a...@arndb.de]
> Sent: Wednesday, May 21, 2014 1:23 PM
> To: Srikanth Thokala
> Cc: Bjorn Helgaas; will.dea...@arm.com; Michal Simek; linux-
> ker...@vger.kernel.org; linux-...@vger.kernel.org
> Subject: Re:
Hi Arnd,
On Mon, May 19, 2014 at 10:33 PM, Arnd Bergmann wrote:
> On Sunday 18 May 2014 19:38:45 Srikanth Thokala wrote:
>> +
>> + if (cfg->ops->is_valid_cfg_access) {
>> + if (!cfg->ops->is_valid_cfg_access(bus, devfn)) {
>> +
This patch adds support for a generic CAM and ECAM configuration
space accesses.
Signed-off-by: Srikanth Thokala
---
This patch is created with reference from Will's patch series:
1/3 - "ARM: kconfig: allow PCI support to be selected with ARCH_MULTIPLATFORM"
2/3 - "PCI:
On Wed, May 7, 2014 at 8:05 PM, Arnd Bergmann wrote:
> On Wednesday 07 May 2014 17:21:13 Srikanth Thokala wrote:
>> On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
>> > On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> >> +/**
>> >> + * xilin
On Wed, Apr 30, 2014 at 9:04 PM, Arnd Bergmann wrote:
> On Tuesday 15 April 2014, Srikanth Thokala wrote:
>> +Required properties:
>> +- #address-cells: Address representation for root ports, set to <3>
>> +- #size-cells: Size representation for root ports, set to
On Thu, May 1, 2014 at 3:11 AM, Bjorn Helgaas wrote:
> On Tue, Apr 15, 2014 at 05:08:31PM +0530, Srikanth Thokala wrote:
>> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>>
>> Signed-off-by: Srikanth Thokala
>> ---
>> Changes in v3:
>> - Rebase
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Acked-by: Jassi Brar
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and w
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
Acked-by: Rob Herring
---
Changes in v8:
Fixed typos as suggested by Rob, Thanks.
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2
Hi,
Kindly review the driver and please let me know if you have any comments.
Thanks
Srikanth
On Tue, Apr 15, 2014 at 5:08 PM, Srikanth Thokala wrote:
> This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
>
> Signed-off-by: Srikanth Thokala
> ---
> Changes in v3:
> -
On Wed, Apr 16, 2014 at 5:01 PM, Vinod Koul wrote:
> On Tue, Apr 01, 2014 at 05:57:04PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory acce
On Wed, Apr 16, 2014 at 3:56 PM, Vinod Koul wrote:
> On Wed, Apr 16, 2014 at 03:41:34PM +0530, Srikanth Thokala wrote:
>> On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
>> > On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> >> This is the d
On Wed, Apr 16, 2014 at 2:36 PM, Vinod Koul wrote:
> On Fri, Mar 28, 2014 at 05:33:42PM +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct
This is the driver for Xilinx AXI PCIe Host Bridge Soft IP
Signed-off-by: Srikanth Thokala
---
Changes in v3:
- Rebased on v3.15.0-rc1
- Added support for interrupt-map DT functionality.
- Removed map_irq() wrapper, instead using of_irq_parse_and_map_pci().
- Modified resource mapping logic as
Hi Jonathan,
On Tue, Apr 8, 2014 at 8:14 PM, Jonathan Corbet wrote:
> On Mon, 7 Apr 2014 20:22:54 +0530
> Srikanth Thokala wrote:
>
>> Kindly review this driver and please let me know if you have any comments.
>
> Here's some comments from a quick look at the patch;
Hi,
Kindly review this driver and please let me know if you have any comments.
Thanks
Srikanth
On Mon, Mar 31, 2014 at 7:24 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Central Direct Memory Access (AXI
> CDMA) core, which is a soft Xilinx IP core that provides high-ban
Hi,
Kindly review this driver patch and please let me know if you have any comments.
Srikanth
On Tue, Apr 1, 2014 at 5:57 PM, Srikanth Thokala wrote:
> This is the driver for the AXI Direct Memory Access (AXI DMA)
> core, which is a soft Xilinx IP core that provides high-
> bandwid
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v2:
None
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx
: Srikanth Thokala
---
Note:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
Changes in v2:
- Simplified the logi
Microblaze platforms.
Signed-off-by: Srikanth Thokala
---
NOTE:
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-
Device-tree binding documentation of Xilinx Central DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_cdma.txt | 54
1 file changed, 54 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_cdma.txt
On Mon, Mar 31, 2014 at 3:00 PM, Andy Shevchenko
wrote:
> On Sat, 2014-03-29 at 20:58 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Direct Memory Access (AXI DMA)
>> core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct memory acce
: Srikanth Thokala
---
- This driver patch is created on top of earlier series,
1/2 - "dma: Add Xilinx Video DMA DT Binding Documentation"
2/2 - "dma: Add Xilinx AXI Video Direct Memory Access Engine driver support"
- Rebased on v3.14.0-rc8
---
drivers/dma/Kconfig |
Device-tree binding documentation of Xilinx DMA Engine
Signed-off-by: Srikanth Thokala
---
.../devicetree/bindings/dma/xilinx/xilinx_dma.txt | 65
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/dma/xilinx/xilinx_dma.txt
diff --git
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Acked-by: Jassi Brar
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and w
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v7:
None
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly
design
http://www.wiki.xilinx.com/Zynq+Base+TRD+14.5
2. Common Display Framework
http://events.linuxfoundation.org/sites/events/files/slides/20131024-elce.pdf
Regards,
Srikanth
Changes in v7:
- Fixed minor comments suggested by Jaswinder, Thanks.
Changes in v6:
- Fixed minor comments
On Mon, Mar 24, 2014 at 8:53 PM, Jassi Brar wrote:
> On Mon, Mar 24, 2014 at 8:44 PM, Srikanth Thokala wrote:
>> On Mon, Mar 24, 2014 at 4:21 PM, Jassi Brar
>> wrote:
>>> On 24 March 2014 14:30, Srikanth Thokala wrote:
>>>> Hi Jassi,
>>>>
>&g
On Mon, Mar 24, 2014 at 4:21 PM, Jassi Brar wrote:
> On 24 March 2014 14:30, Srikanth Thokala wrote:
>> Hi Jassi,
>>
>> Thanks for the Acked-by.
>>
>> On Mon, Mar 24, 2014 at 11:50 AM, Jassi Brar
>> wrote:
>>> On Tue, Mar 18
Hi Jassi,
Thanks for the Acked-by.
On Mon, Mar 24, 2014 at 11:50 AM, Jassi Brar wrote:
> On Tue, Mar 18, 2014 at 12:36 AM, Srikanth Thokala wrote:
>
>> +
>> +/**
>> + * xilinx_vdma_prep_slave_sg - prepare a descriptor for a DMA_SLAVE
>
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
design
http://www.wiki.xilinx.com/Zynq+Base+TRD+14.5
2. Common Display Framework
http://events.linuxfoundation.org/sites/events/files/slides/20131024-elce.pdf
Regards,
Srikanth
Changes in v6:
- Fixed minor comments suggested by Andy, Thanks.
Changes in v5:
- Modified to accept only 1 frame
Device-tree binding documentation of Xilinx Video DMA Engine
Signed-off-by: Srikanth Thokala
---
Changes in v6:
None
Changes in v5:
None
Changes in v4:
None
Changes in v3:
None
Changes in v2:
- Removed device-id DT property, as suggested by Arnd Bergmann
- Properly documented DT bindings as
On Sat, Mar 15, 2014 at 12:11 AM, Andy Shevchenko
wrote:
> On Fri, 2014-03-14 at 23:20 +0530, Srikanth Thokala wrote:
>> This is the driver for the AXI Video Direct Memory Access (AXI
>> VDMA) core, which is a soft Xilinx IP core that provides high-
>> bandwidth direct
asynchronous read
and write channel operation.
This module works on Zynq (ARM Based SoC) and Microblaze platforms.
Signed-off-by: Srikanth Thokala
Reviewed-by: Levente Kurusa
---
NOTE:
- Created a separate directory 'dma/xilinx' as Xilinx has two more
DMA IPs and we are also planning t
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