From: Suravee Suthikulpanit
Since PCIe is using SMMUv1 which only supports 15-bit stream ID,
only 7-bit PCI bus id is used to specify stream ID. Therefore,
we only limit the PCI bus range to 0x7f.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 2 +-
1
From: Suravee Suthikulpanit
AMD Seattle should support 40-bit DMA.
Signed-off-by: Suravee Suthikulpanit
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi
From: Suravee Suthikulpanit
This patch set mainly fixes up the dma-ranges and pci bus range.
Please see each patch for more details.
Suravee Suthikulpanit (2):
arm64: amd-seattle: Fix dma-ranges property
arm64: amd-seattle: Fix PCI bus range due to SMMU limitation
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set mainly fixes up the dma-ranges and pci bus range.
Please see each patch for more details.
Suravee Suthikulpanit (2):
arm64: amd-seattle: Fix dma-ranges property
arm64: amd-seattle: Fix PCI bus range due to SMMU
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
AMD Seattle should support 40-bit DMA.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Since PCIe is using SMMUv1 which only supports 15-bit stream ID,
only 7-bit PCI bus id is used to specify stream ID. Therefore,
we only limit the PCI bus range to 0x7f.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle Development platform.
Cc: Arnd Bergmann
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
V5
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle Development platform.
Cc: Arnd Bergmann a...@arndb.de
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform.
Cc: Arnd Bergmann
Cc: Marc Zyngier
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
V4 Changes:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform.
Cc: Arnd Bergmann a...@arndb.de
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas
From: Suravee Suthikulpanit
This patch checks if the parent domain is NULL before recursively freeing
irqs in the parent domains.
In this case, GICv2m is freeing irqs in parent (GIC), which calls
irq_domain_free_irqs_top. This fixes the crash below:
Unble to handle kernel NULL pointer
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch checks if the parent domain is NULL before recursively freeing
irqs in the parent domains.
In this case, GICv2m is freeing irqs in parent (GIC), which calls
irq_domain_free_irqs_top. This fixes the crash below:
Unble to handle
From: Suravee Suthikulpanit
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
and the referenced by PCI
From: Suravee Suthikulpanit
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
pci/host-generic
Changes from
From: Suravee Suthikulpanit
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it implements and registers set_msi_parent callback.
Cc: Bjorn Helgass
Cc: Liviu Dudau
Cc: Will Deacon
Cc:
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch introduces a new DT binding, msi-parent, which can
be used to specify MSI-parent phandle for a particular PCI
generic host controller.
Also, it implements and registers set_msi_parent callback.
Cc: Bjorn Helgass
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
From: Suravee Suthikulpanit
This patch implement set_msi_parent callback for PCI generic host controller.
Cc: Bjorn Helgass
Cc: Liviu Dudau
Cc: Lorenzo Pieralisi
Signed-off-by: Suravee Suthikulpanit
---
drivers/pci/host/pci-host-generic.c | 14 ++
1 file changed, 14
From: Suravee Suthikulpanit
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
and the referenced by PCI
From: Suravee Suthikulpanit
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
pci/host-generic
Suravee
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces a new callback function to allow PCI host drivers
to specify MSI controller to be used for the child buses / devices.
This is reabased from:
git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch implement set_msi_parent callback for PCI generic host controller.
Cc: Bjorn Helgass bhelg...@google.com
Cc: Liviu Dudau liviu.du...@arm.com
Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com
Signed-off-by: Suravee Suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
In the pci_scan_root_bus, pci_bus is created and passed down to:
pci_scan_child_bus
pci_scan_bridge
pci_add_new_bus
pci_alloc_child_bus
In pci_alloc_child_bus, the parent's msi_chip is propagated to child,
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch adopt the new hierarchy irq domain, and is rebased from:
Git tree :
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch adopt the new hierarchy irq domain, and is rebased from:
Git tree :
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch set is rebased from:
Git tree :
git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git
Git branch :
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This patch set is rebased from:
Git tree :
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Add a helper function to set irq type in parent irq domain.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
---
include/linux/irq.h | 1 +
kernel/irq/chip.c | 10 ++
2 files changed, 11 insertions(+)
diff
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
Change in V3:
* Change sata compatible-id to
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Suravee Suthikulpanit
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Rob Herring
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
Change in V2:
* Re-order
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Suravee
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Cc: Rob Herring
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
arch/arm64/Kconfig
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Cc: Rob Herring robh...@kernel.org
Signed-off-by: Suravee
From: Suravee Suthikulpanit
Initial revision of device tree for AMD Seattle platform
Cc: Rob Herring
Cc: Mark Rutland
Cc: Will Deacon
Cc: Catalin Marinas
Signed-off-by: Suravee Suthikulpanit
Signed-off-by: Thomas Lendacky
Signed-off-by: Joel Schopp
---
arch/arm64/boot/dts/Makefile
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
When specify PCI_PROBE_ONLY, the resource parent does not get assigned.
Therefore, pci_enable_resources() return error saying that
"BAR x not claimed".
Note: This same logic is also used in the arch/arm/kernel/bios32.c
Cc: Liviu Dudau
Cc: Bjorn Helgaas
Cc: Will
From: Suravee Suthikulpanit
This is an RFC to introduce support for AMD Seattle ARM64 platform.
It is also intended to provide support for validating Liviu's PCI patch series:
[PATCH v12 00/12] Support for creating generic PCI host bridges from DT
https://lkml.org/lkml/2014/9/23/852
It
From: Suravee Suthikulpanit
This patch adds ARM64 support to the generic PCI host driver.
For MSI support, it adds new device tree binding "msi-parent",
which should point to corresponded msi-controller.
Cc: Will Deacon
Cc: Liviu Dudau
Cc: Bjorn Helgaas
Cc: Mark Rutland
Cc: Catalin Marinas
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This is an RFC to introduce support for AMD Seattle ARM64 platform.
It is also intended to provide support for validating Liviu's PCI patch series:
[PATCH v12 00/12] Support for creating generic PCI host bridges from DT
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds ARM64 support to the generic PCI host driver.
For MSI support, it adds new device tree binding msi-parent,
which should point to corresponded msi-controller.
Cc: Will Deacon will.dea...@arm.com
Cc: Liviu Dudau
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
When specify PCI_PROBE_ONLY, the resource parent does not get assigned.
Therefore, pci_enable_resources() return error saying that
BAR x not claimed.
Note: This same logic is also used in the arch/arm/kernel/bios32.c
Cc: Liviu Dudau
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Initial revision of device tree for AMD Seattle platform
Cc: Rob Herring robh...@kernel.org
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Will Deacon will.dea...@arm.com
Cc: Catalin Marinas catalin.mari...@arm.com
Signed-off-by: Suravee
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Signed-off-by: Suravee Suthikulpanit
Acked-by: Marc Zyngier
Cc: Mark Rutland
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v11 00/10] Support for
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec 1.
Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
Acked-by: Marc Zyngier marc.zyng...@arm.com
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
From: Suravee Suthikulpanit
NOTE: Resend w/ proper subject for the 2/2 patch.
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports
From: Suravee Suthikulpanit
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc: Catalin Marinas
Cc: Will Deacon
Signed-off-by: Suravee Suthikulpanit
---
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH v10 00/10] Support for
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
[PATCH
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec 1.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Jason Cooper
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch implelments the ARM64 version of arch_setup_msi_irqs(),
which does not return 1 for when PCI_CAP_ID_MSI and nvec 1.
Cc: Mark Rutland mark.rutl...@arm.com
Cc: Marc Zyngier marc.zyng...@arm.com
Cc: Jason Cooper
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
NOTE: Resend w/ proper subject for the 2/2 patch.
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit
As a follow up of the email thread:
[PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1
https://lkml.org/lkml/2014/9/1/446
Besides Hanjun Guo's patches above, these are the additional patches required
to boot AMD Seattle platform with full ACPI
From: Mark Salter
Commit 86c8b27a01cf:
"arm64: ignore DT memreserve entries when booting in UEFI mode
prevents early_init_fdt_scan_reserved_mem() from being called for
arm64 kernels booting via UEFI. This was done because the kernel
will use the UEFI memory map to determine reserved memory
From: Ard Biesheuvel
If we cannot relocate the kernel Image to its preferred offset of base of DRAM
plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus
TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still
proceed normally otherwise.
Acked-by:
From: Grame Gregory
This is a subset of pl011 UART which does not supprt DMA or baud rate
changing.
It is specified in the Server Base System Architecture document from
ARM.
Signed-off-by: Graeme Gregory
---
drivers/tty/Kconfig| 6 +
drivers/tty/Makefile | 1 +
From: Suravee Suthikulpanit
This patch adds ACPI match table in ahci_platform. The table includes
the acpi_device_id to match AMD Seattle SATA controller with following
asl structure in DSDT:
Device (SATA0)
{
Name(_HID, "AMDI0600")// Seattle AHSATA
Name (_CCA, 1)
From: Ard Biesheuvel ard.biesheu...@linaro.org
If we cannot relocate the kernel Image to its preferred offset of base of DRAM
plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus
TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still
proceed normally
From: Grame Gregory graeme.greg...@linaro.org
This is a subset of pl011 UART which does not supprt DMA or baud rate
changing.
It is specified in the Server Base System Architecture document from
ARM.
Signed-off-by: Graeme Gregory graeme.greg...@linaro.org
---
drivers/tty/Kconfig| 6 +
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds ACPI match table in ahci_platform. The table includes
the acpi_device_id to match AMD Seattle SATA controller with following
asl structure in DSDT:
Device (SATA0)
{
Name(_HID, AMDI0600)// Seattle AHSATA
From: Mark Salter msal...@redhat.com
Commit 86c8b27a01cf:
arm64: ignore DT memreserve entries when booting in UEFI mode
prevents early_init_fdt_scan_reserved_mem() from being called for
arm64 kernels booting via UEFI. This was done because the kernel
will use the UEFI memory map to determine
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
As a follow up of the email thread:
[PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1
https://lkml.org/lkml/2014/9/1/446
Besides Hanjun Guo's patches above, these are the additional patches required
to boot AMD Seattle
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc:
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec 1.
Cc: Mark Rutland
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc:
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the following patch set which
implements PCI supports for ARM64:
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec 1.
Cc: Mark Rutland
From: Suravee Suthikulpanit
This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver.
It adds ACPI matching table in ahci_platform to support AMD Seattle SATA
controller
with following ASL structure in DSDT:
Device (SATA0)
{
Name(_HID, "AMDI0600")//
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver.
It adds ACPI matching table in ahci_platform to support AMD Seattle SATA
controller
with following ASL structure in DSDT:
Device (SATA0)
{
From: Suravee Suthikulpanit
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec > 1.
Cc: Mark Rutland
Cc: Marc Zyngier
Cc: Jason Cooper
Cc:
From: Suravee Suthikulpanit
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch introduces a new property in
From: Suravee Suthikulpanit
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 of"Add support for PCI in
AArch64"
(https://lkml.org/lkml/2014/3/14/320).
Changes in V4:
*
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch set introduces support for MSI(-X) in GICv2m specification,
which is implemented in some variation of GIC400.
This depends on and has been tested with the V7 ofAdd support for PCI in
AArch64
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
ARM GICv2m specification extends GICv2 to support MSI(-X) with
a new set of register frame. This patch introduces support for
the non-secure GICv2m register frame. Currently, GICV2m is available
in certain version of GIC-400.
The patch
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com
This patch extend GICv2m MSI to support multiple MSI in ARM64.
This requires the common arch_setup_msi_irqs() to be overwriten
with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and
nvec 1.
Cc: Mark Rutland
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