[PATCH 2/2] arm64: amd-seattle: Fix PCI bus range due to SMMU limitation

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Since PCIe is using SMMUv1 which only supports 15-bit stream ID, only 7-bit PCI bus id is used to specify stream ID. Therefore, we only limit the PCI bus range to 0x7f. Signed-off-by: Suravee Suthikulpanit --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 2 +- 1

[PATCH 1/2] arm64: amd-seattle: Fix dma-ranges property

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit AMD Seattle should support 40-bit DMA. Signed-off-by: Suravee Suthikulpanit --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi

[PATCH 0/2] arm64: amd-seattle: Misceleneous DT fix up

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set mainly fixes up the dma-ranges and pci bus range. Please see each patch for more details. Suravee Suthikulpanit (2): arm64: amd-seattle: Fix dma-ranges property arm64: amd-seattle: Fix PCI bus range due to SMMU limitation

[PATCH 0/2] arm64: amd-seattle: Misceleneous DT fix up

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set mainly fixes up the dma-ranges and pci bus range. Please see each patch for more details. Suravee Suthikulpanit (2): arm64: amd-seattle: Fix dma-ranges property arm64: amd-seattle: Fix PCI bus range due to SMMU

[PATCH 1/2] arm64: amd-seattle: Fix dma-ranges property

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com AMD Seattle should support 40-bit DMA. Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com --- arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 +++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git

[PATCH 2/2] arm64: amd-seattle: Fix PCI bus range due to SMMU limitation

2014-11-30 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Since PCIe is using SMMUv1 which only supports 15-bit stream ID, only 7-bit PCI bus id is used to specify stream ID. Therefore, we only limit the PCI bus range to 0x7f. Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com

[PATCH V5] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-11-25 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle Development platform. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- V5

[PATCH V5] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-11-25 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle Development platform. Cc: Arnd Bergmann a...@arndb.de Cc: Marc Zyngier marc.zyng...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas

[PATCH V4] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-11-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle platform. Cc: Arnd Bergmann Cc: Marc Zyngier Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- V4 Changes:

[PATCH V4] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-11-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle platform. Cc: Arnd Bergmann a...@arndb.de Cc: Marc Zyngier marc.zyng...@arm.com Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas

[PATCH] irqdomain: Fix NULL pointer dererence in irq_domain_free_irqs_parent

2014-11-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch checks if the parent domain is NULL before recursively freeing irqs in the parent domains. In this case, GICv2m is freeing irqs in parent (GIC), which calls irq_domain_free_irqs_top. This fixes the crash below: Unble to handle kernel NULL pointer

[PATCH] irqdomain: Fix NULL pointer dererence in irq_domain_free_irqs_parent

2014-11-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch checks if the parent domain is NULL before recursively freeing irqs in the parent domains. In this case, GICv2m is freeing irqs in parent (GIC), which calls irq_domain_free_irqs_top. This fixes the crash below: Unble to handle

[PATCH V2 1/2] PCI: Add new pci_ops for setting MSI parent for PCI bus

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit In the pci_scan_root_bus, pci_bus is created and passed down to: pci_scan_child_bus pci_scan_bridge pci_add_new_bus pci_alloc_child_bus In pci_alloc_child_bus, the parent's msi_chip is propagated to child, and the referenced by PCI

[PATCH V2 0/2] PCI: generic: Assiging msi-controller to PCI hostbridge

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces a new callback function to allow PCI host drivers to specify MSI controller to be used for the child buses / devices. This is reabased from: git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-generic Changes from

[PATCH V2 2/2] PCI: generic: Add msi_parent DT binding

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch introduces a new DT binding, msi-parent, which can be used to specify MSI-parent phandle for a particular PCI generic host controller. Also, it implements and registers set_msi_parent callback. Cc: Bjorn Helgass Cc: Liviu Dudau Cc: Will Deacon Cc:

[PATCH V2 2/2] PCI: generic: Add msi_parent DT binding

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch introduces a new DT binding, msi-parent, which can be used to specify MSI-parent phandle for a particular PCI generic host controller. Also, it implements and registers set_msi_parent callback. Cc: Bjorn Helgass

[PATCH V2 0/2] PCI: generic: Assiging msi-controller to PCI hostbridge

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces a new callback function to allow PCI host drivers to specify MSI controller to be used for the child buses / devices. This is reabased from: git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git

[PATCH V2 1/2] PCI: Add new pci_ops for setting MSI parent for PCI bus

2014-11-11 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com In the pci_scan_root_bus, pci_bus is created and passed down to: pci_scan_child_bus pci_scan_bridge pci_add_new_bus pci_alloc_child_bus In pci_alloc_child_bus, the parent's msi_chip is propagated to child,

[PATCH 2/2] PCI: generic: Add set_msi_parent callback

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch implement set_msi_parent callback for PCI generic host controller. Cc: Bjorn Helgass Cc: Liviu Dudau Cc: Lorenzo Pieralisi Signed-off-by: Suravee Suthikulpanit --- drivers/pci/host/pci-host-generic.c | 14 ++ 1 file changed, 14

[PATCH 1/2] PCI: Add new pci_ops for setting MSI parent for PCI bus

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit In the pci_scan_root_bus, pci_bus is created and passed down to: pci_scan_child_bus pci_scan_bridge pci_add_new_bus pci_alloc_child_bus In pci_alloc_child_bus, the parent's msi_chip is propagated to child, and the referenced by PCI

[PATCH 0/2] PCI: generic: Assiging msi-controller to PCI hostbridge

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces a new callback function to allow PCI host drivers to specify MSI controller to be used for the child buses / devices. This is reabased from: git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git pci/host-generic Suravee

[PATCH 0/2] PCI: generic: Assiging msi-controller to PCI hostbridge

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces a new callback function to allow PCI host drivers to specify MSI controller to be used for the child buses / devices. This is reabased from: git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git

[PATCH 2/2] PCI: generic: Add set_msi_parent callback

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch implement set_msi_parent callback for PCI generic host controller. Cc: Bjorn Helgass bhelg...@google.com Cc: Liviu Dudau liviu.du...@arm.com Cc: Lorenzo Pieralisi lorenzo.pieral...@arm.com Signed-off-by: Suravee Suthikulpanit

[PATCH 1/2] PCI: Add new pci_ops for setting MSI parent for PCI bus

2014-11-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com In the pci_scan_root_bus, pci_bus is created and passed down to: pci_scan_child_bus pci_scan_bridge pci_add_new_bus pci_alloc_child_bus In pci_alloc_child_bus, the parent's msi_chip is propagated to child,

[V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[V10 PATCH 1/2] genirq: Add irq_chip_set_type_parent function

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Add a helper function to set irq type in parent irq domain. Signed-off-by: Suravee Suthikulpanit --- include/linux/irq.h | 1 + kernel/irq/chip.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index

[V10 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This patch adopt the new hierarchy irq domain, and is rebased from: Git tree :

[V10 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This patch adopt the new hierarchy irq domain, and is rebased from: Git tree :

[V10 PATCH 1/2] genirq: Add irq_chip_set_type_parent function

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Add a helper function to set irq type in parent irq domain. Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com --- include/linux/irq.h | 1 + kernel/irq/chip.c | 10 ++ 2 files changed, 11 insertions(+) diff

[V10 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-11-03 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[V9 PATCH 1/2] genirq: Add irq_chip_set_type_parent function

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Add a helper function to set irq type in parent irq domain. Signed-off-by: Suravee Suthikulpanit --- include/linux/irq.h | 1 + kernel/irq/chip.c | 10 ++ 2 files changed, 11 insertions(+) diff --git a/include/linux/irq.h b/include/linux/irq.h index

[V9 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This patch set is rebased from: Git tree : git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms.git Git branch :

[V9 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[V9 PATCH 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This patch set is rebased from: Git tree :

[V9 PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[V9 PATCH 1/2] genirq: Add irq_chip_set_type_parent function

2014-10-31 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Add a helper function to set irq type in parent irq domain. Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com --- include/linux/irq.h | 1 + kernel/irq/chip.c | 10 ++ 2 files changed, 11 insertions(+) diff

[PATCH V3] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- Change in V3: * Change sata compatible-id to

[PATCH V3] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Suravee Suthikulpanit

[PATCH V2] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-27 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Cc: Rob Herring Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- Change in V2: * Re-order

[PATCH V2] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-27 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas catalin.mari...@arm.com Cc: Rob Herring robh...@kernel.org Signed-off-by: Suravee

[PATCH] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Cc: Rob Herring Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- arch/arm64/Kconfig

[PATCH] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-10-24 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle platform Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas catalin.mari...@arm.com Cc: Rob Herring robh...@kernel.org Signed-off-by: Suravee

[RFC 1/4] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit Initial revision of device tree for AMD Seattle platform Cc: Rob Herring Cc: Mark Rutland Cc: Will Deacon Cc: Catalin Marinas Signed-off-by: Suravee Suthikulpanit Signed-off-by: Thomas Lendacky Signed-off-by: Joel Schopp --- arch/arm64/boot/dts/Makefile

[RFC 4/4] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[RFC 3/4] arm64: Do not call enable PCI resources when specify PCI_PROBE_ONLY

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit When specify PCI_PROBE_ONLY, the resource parent does not get assigned. Therefore, pci_enable_resources() return error saying that "BAR x not claimed". Note: This same logic is also used in the arch/arm/kernel/bios32.c Cc: Liviu Dudau Cc: Bjorn Helgaas Cc: Will

[RFC 0/4] Add PCI/MSI(x) support for AMD Seattle Platform

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This is an RFC to introduce support for AMD Seattle ARM64 platform. It is also intended to provide support for validating Liviu's PCI patch series: [PATCH v12 00/12] Support for creating generic PCI host bridges from DT https://lkml.org/lkml/2014/9/23/852 It

[RFC 2/4] PCI: generic: Add support for ARM64 and MSI(x)

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch adds ARM64 support to the generic PCI host driver. For MSI support, it adds new device tree binding "msi-parent", which should point to corresponded msi-controller. Cc: Will Deacon Cc: Liviu Dudau Cc: Bjorn Helgaas Cc: Mark Rutland Cc: Catalin Marinas

[RFC 0/4] Add PCI/MSI(x) support for AMD Seattle Platform

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This is an RFC to introduce support for AMD Seattle ARM64 platform. It is also intended to provide support for validating Liviu's PCI patch series: [PATCH v12 00/12] Support for creating generic PCI host bridges from DT

[RFC 2/4] PCI: generic: Add support for ARM64 and MSI(x)

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch adds ARM64 support to the generic PCI host driver. For MSI support, it adds new device tree binding msi-parent, which should point to corresponded msi-controller. Cc: Will Deacon will.dea...@arm.com Cc: Liviu Dudau

[RFC 3/4] arm64: Do not call enable PCI resources when specify PCI_PROBE_ONLY

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com When specify PCI_PROBE_ONLY, the resource parent does not get assigned. Therefore, pci_enable_resources() return error saying that BAR x not claimed. Note: This same logic is also used in the arch/arm/kernel/bios32.c Cc: Liviu Dudau

[RFC 1/4] arm64: amd-seattle: Adding device tree for AMD Seattle platform

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Initial revision of device tree for AMD Seattle platform Cc: Rob Herring robh...@kernel.org Cc: Mark Rutland mark.rutl...@arm.com Cc: Will Deacon will.dea...@arm.com Cc: Catalin Marinas catalin.mari...@arm.com Signed-off-by: Suravee

[RFC 4/4] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-28 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[V8 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[V8 1/2] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1. Signed-off-by: Suravee Suthikulpanit Acked-by: Marc Zyngier Cc: Mark Rutland Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon

[V8 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: [PATCH v11 00/10] Support for

[V8 1/2] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec 1. Signed-off-by: Suravee Suthikulpanit suravee.suthikulpa...@amd.com Acked-by: Marc Zyngier marc.zyng...@arm.com

[V8 0/2] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: [PATCH

[V8 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-20 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[PATCH 2/2 V7] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suravee Suthikulpanit ---

[PATCH 0/2 V7] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit NOTE: Resend w/ proper subject for the 2/2 patch. This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports

[PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc: Catalin Marinas Cc: Will Deacon Signed-off-by: Suravee Suthikulpanit ---

[PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[PATCH 0/2 V7] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: [PATCH v10 00/10] Support for

[PATCH 0/2 V7] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: [PATCH

[PATCH 2/2] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec 1. Cc: Mark Rutland mark.rutl...@arm.com Cc: Marc Zyngier marc.zyng...@arm.com Cc: Jason Cooper

[PATCH 1/2 V7] irqchip: gic: Add support for multiple MSI for ARM64

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch implelments the ARM64 version of arch_setup_msi_irqs(), which does not return 1 for when PCI_CAP_ID_MSI and nvec 1. Cc: Mark Rutland mark.rutl...@arm.com Cc: Marc Zyngier marc.zyng...@arm.com Cc: Jason Cooper

[PATCH 0/2 V7] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com NOTE: Resend w/ proper subject for the 2/2 patch. This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set

[PATCH 2/2 V7] irqchip: gicv2m: Add supports for ARM GICv2m MSI(-X)

2014-09-17 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[RFC PATCH for AMD Seattle 0/4] Drivers for AMD-Seatlle to boot from ACPI

2014-09-15 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit As a follow up of the email thread: [PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1 https://lkml.org/lkml/2014/9/1/446 Besides Hanjun Guo's patches above, these are the additional patches required to boot AMD Seattle platform with full ACPI

[PATCH 3/4] efi/arm64: fix fdt-related memory reservation

2014-09-15 Thread suravee.suthikulpanit
From: Mark Salter Commit 86c8b27a01cf: "arm64: ignore DT memreserve entries when booting in UEFI mode prevents early_init_fdt_scan_reserved_mem() from being called for arm64 kernels booting via UEFI. This was done because the kernel will use the UEFI memory map to determine reserved memory

[PATCH 2/4] arm64/efi: efistub: don't abort if base of DRAM is occupied

2014-09-15 Thread suravee.suthikulpanit
From: Ard Biesheuvel If we cannot relocate the kernel Image to its preferred offset of base of DRAM plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still proceed normally otherwise. Acked-by:

[PATCH 4/4] [RFC PATCH for Juno 2/2] tty: SBSA compatible UART

2014-09-15 Thread suravee.suthikulpanit
From: Grame Gregory This is a subset of pl011 UART which does not supprt DMA or baud rate changing. It is specified in the Server Base System Architecture document from ARM. Signed-off-by: Graeme Gregory --- drivers/tty/Kconfig| 6 + drivers/tty/Makefile | 1 +

[PATCH 1/4] ata: ahci_platform: Add ACPI support for AMD Seattle SATA controller

2014-09-15 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch adds ACPI match table in ahci_platform. The table includes the acpi_device_id to match AMD Seattle SATA controller with following asl structure in DSDT: Device (SATA0) { Name(_HID, "AMDI0600")// Seattle AHSATA Name (_CCA, 1)

[PATCH 2/4] arm64/efi: efistub: don't abort if base of DRAM is occupied

2014-09-15 Thread suravee.suthikulpanit
From: Ard Biesheuvel ard.biesheu...@linaro.org If we cannot relocate the kernel Image to its preferred offset of base of DRAM plus TEXT_OFFSET, instead relocate it to the lowest available 2 MB boundary plus TEXT_OFFSET. We may lose a bit of memory at the low end, but we can still proceed normally

[PATCH 4/4] [RFC PATCH for Juno 2/2] tty: SBSA compatible UART

2014-09-15 Thread suravee.suthikulpanit
From: Grame Gregory graeme.greg...@linaro.org This is a subset of pl011 UART which does not supprt DMA or baud rate changing. It is specified in the Server Base System Architecture document from ARM. Signed-off-by: Graeme Gregory graeme.greg...@linaro.org --- drivers/tty/Kconfig| 6 +

[PATCH 1/4] ata: ahci_platform: Add ACPI support for AMD Seattle SATA controller

2014-09-15 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch adds ACPI match table in ahci_platform. The table includes the acpi_device_id to match AMD Seattle SATA controller with following asl structure in DSDT: Device (SATA0) { Name(_HID, AMDI0600)// Seattle AHSATA

[PATCH 3/4] efi/arm64: fix fdt-related memory reservation

2014-09-15 Thread suravee.suthikulpanit
From: Mark Salter msal...@redhat.com Commit 86c8b27a01cf: arm64: ignore DT memreserve entries when booting in UEFI mode prevents early_init_fdt_scan_reserved_mem() from being called for arm64 kernels booting via UEFI. This was done because the kernel will use the UEFI memory map to determine

[RFC PATCH for AMD Seattle 0/4] Drivers for AMD-Seatlle to boot from ACPI

2014-09-15 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com As a follow up of the email thread: [PATCH v3 00/17] Introduce ACPI for ARM64 based on ACPI 5.1 https://lkml.org/lkml/2014/9/1/446 Besides Hanjun Guo's patches above, these are the additional patches required to boot AMD Seattle

[PATCH 2/2 V6] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc:

[PATCH 1/2 V6] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[PATCH 0/2 V6] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: *

[PATCH 0/2 V6] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: *

[PATCH 1/2 V6] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[PATCH 2/2 V6] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-09-14 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec 1. Cc: Mark Rutland

[PATCH 2/2 V5] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc:

[PATCH 1/2 V5] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[PATCH 0/2 V5] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: *

[PATCH 0/2 V5] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the following patch set which implements PCI supports for ARM64: *

[PATCH 1/2 V5] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[PATCH 2/2 V5] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-09-10 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec 1. Cc: Mark Rutland

[PATCH] ata: ahci_platform: Add ACPI support for AMD Seattle SATA controller

2014-09-09 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver. It adds ACPI matching table in ahci_platform to support AMD Seattle SATA controller with following ASL structure in DSDT: Device (SATA0) { Name(_HID, "AMDI0600")//

[PATCH] ata: ahci_platform: Add ACPI support for AMD Seattle SATA controller

2014-09-09 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch adds ACPI support for non-PCI SATA contoller in ahci_platform driver. It adds ACPI matching table in ahci_platform to support AMD Seattle SATA controller with following ASL structure in DSDT: Device (SATA0) {

[PATCH 2/2 V4] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec > 1. Cc: Mark Rutland Cc: Marc Zyngier Cc: Jason Cooper Cc:

[PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch introduces a new property in

[PATCH 0/2 V4] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the V7 of"Add support for PCI in AArch64" (https://lkml.org/lkml/2014/3/14/320). Changes in V4: *

[PATCH 0/2 V4] irqchip: gic: Introduce ARM GICv2m MSI(-X) support

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch set introduces support for MSI(-X) in GICv2m specification, which is implemented in some variation of GIC400. This depends on and has been tested with the V7 ofAdd support for PCI in AArch64

[PATCH 1/2 V4] irqchip: gic: Add supports for ARM GICv2m MSI(-X)

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com ARM GICv2m specification extends GICv2 to support MSI(-X) with a new set of register frame. This patch introduces support for the non-secure GICv2m register frame. Currently, GICV2m is available in certain version of GIC-400. The patch

[PATCH 2/2 V4] irqchip: gicv2m: Add support for multiple MSI for ARM64 GICv2m

2014-08-13 Thread suravee.suthikulpanit
From: Suravee Suthikulpanit suravee.suthikulpa...@amd.com This patch extend GICv2m MSI to support multiple MSI in ARM64. This requires the common arch_setup_msi_irqs() to be overwriten with ARM64 version which does not return 1 for PCI_CAP_ID_MSI and nvec 1. Cc: Mark Rutland

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