dma-coherent property for PCIe Root

buffers will be hardware coherent if RC driver exposes dma-coherent property ? Regards, Valmiki

Re: Difference between IOVA and bus address when SMMU is enabled

On Sat, May 12, 2018 at 06:25:13PM +0530, valmiki wrote: Hi All, What is the difference between IOVA address and bus address when SMMU is enabled ? Is IOVA address term used only when hypervisor is present ? IOVA = IO virtual address. IOVA is the term normally used to describe the address

Difference between IOVA and bus address when SMMU is enabled

Hi All, What is the difference between IOVA address and bus address when SMMU is enabled ? Is IOVA address term used only when hypervisor is present ? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Re: Affinity for GIC irq line

On 25/04/18 04:23, valmiki wrote: Hi all, When an IRQ line is set affinity using irq_set_affinity, which calls irq_do_set_affinity, this API copies affinity mask to affinity variable in irq_common_data of this irq descriptor. It does a wee bit more. Crucially, it contains the line

Affinity for GIC irq line

asm_do_IRQ run ? For every interrupt this runs on CPU0 and then FIQ/IRQ handling is scheduled on different CPU as per affinity ? How the respective irq line handler is handled on specific CPU core ? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus softw

Re: Why two irq chips for MSI

On 21/03/18 17:12, valmiki wrote: Hi, In most of the RP drivers, why two irq chips are being used for MSI ? One at irq_domain_set_info (which uses irq_compose_msi_msg and irq_set_affinity methods) and another being registered with struct msi_domain_info (which uses irq_mask/irq_unmask methods

Why two irq chips for MSI

w.r.t to virq ? Thanks, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Affinity on non MSI-X interrupts

traffic ? Will this handler ever come out? wont this stall CPU ? Will the interrupts be routed to different CPU's in this case also? Regards, Valmiki --- This email has been checked for viruses by Avast antivirus software. https://www.avast.com/antivirus

Re: Purpose of PCI address in ranges property

On 3/20/2017 3:15 AM, Arnd Bergmann wrote: On Sun, Mar 19, 2017 at 3:14 PM, valmiki wrote: Hi, When ranges property is being parsed using of_pci_get_host_bridge_resources, the pci address is being used for calculating the offset for pci_add_resource_offset. What is this offset for ? So the

Purpose of PCI address in ranges property

& Regards, Valmiki

Can EP bars be called as device memory ?

Hi, In ARMv8 TRM: An unaligned access to any type of Device memory causes an Alignment fault. What is meant by device memory ? Can we call PCIe BAR memory on End point cards as device memory ? Thanks, valmiki

Need clarity on legacy RC interrupt handling

Hi, Legacy interrupts are level triggered, but i see some RC drivers use flow handler "handle_simple_irq" instead why they are not using "handle_level_irq" ? Why they are registering dummy_irq_chip with "handle_simple_irq", if they use this chip how the irq type is set for this virtual irq (

Re: Need clarity on MSI handling in RC driver

Thanks Marc On 1/4/2017 11:16 PM, Marc Zyngier wrote: On 04/01/17 17:39, valmiki wrote: Hi All, I have a doubt, the MSI domains are handled differently in different RC drivers. Some drivers use irq_domain_add_linear alone, and some use pci_msi_create_irq_domain also to handle MSI. In most

Need clarity on MSI handling in RC driver

both pci_msi_create_irq_domain and irq_domain_add_linear are used. So is this because of architecture difference between ARM and ARM64 ? Thanks & Regards, valmiki

Re: Need clarity on PCIe MSI interrupt in device tree

Thanks Mark On 1/4/2017 3:35 PM, Mark Rutland wrote: On Wed, Jan 04, 2017 at 08:47:43AM +0530, valmiki wrote: Hi, Hi, I have confusion on MSI interrupt flags in PCIe documetation. MSI interrupts are edge triggered, but i see some controllers use Ex:tegra <0 99 0x4>, here interrupt

Re: Need clarity on PCIe MSI interrupt in device tree

Thans Marc On 1/4/2017 1:59 PM, Marc Zyngier wrote: On 04/01/17 03:17, valmiki wrote: Hi, I have confusion on MSI interrupt flags in PCIe documetation. MSI interrupts are edge triggered, but i see some controllers use Ex:tegra <0 99 0x4>, here interrupt flags show 0x4 which means

Need clarity on PCIe MSI interrupt in device tree

t like this, why MSI depicted as level sensitive in device tree. Regards, valmiki