Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

writeb(value, PCI_IOBASE + addr); else if (arm64_extio_ops->pfout) arm64_extio_ops->pfout(arm64_extio_ops->devpara, addr + arm64_extio_ops->ptoffset, , sizeof(u8), 1); } here, arm64_extio_ops->ptoffset is the offset between the real legacy IO address and the logical IO address, similar to the offset of primary address and secondary address in PCI bridge. But in V3, LPC driver call pci_address_to_pio to request the logical IO as PCI host bridge during its probing. cheers, Zhichang > > Arnd >

Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

writeb(value, PCI_IOBASE + addr); else if (arm64_extio_ops->pfout) arm64_extio_ops->pfout(arm64_extio_ops->devpara, addr + arm64_extio_ops->ptoffset, , sizeof(u8), 1); } here, arm64_extio_ops->ptoffset is the offset between the real legacy IO address and the logical IO address, similar to the offset of primary address and secondary address in PCI bridge. But in V3, LPC driver call pci_address_to_pio to request the logical IO as PCI host bridge during its probing. cheers, Zhichang > > Arnd >

Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

nother alternative that just occurred to me would be to move > the pci_address_to_pio() call from __of_address_to_resource() > into of_bus_pci_translate() and then do the special handling > for the ISA/LPC bus in of_bus_isa_translate(). As for this idea, do you mean that of_translate_address will directly return the final logical IO start address?? It seems to extend the definition of of_translate_address. Thanks, Zhichang > > Arnd >

Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

nother alternative that just occurred to me would be to move > the pci_address_to_pio() call from __of_address_to_resource() > into of_bus_pci_translate() and then do the special handling > for the ISA/LPC bus in of_bus_isa_translate(). As for this idea, do you mean that of_translate_address will directly return the final logical IO start address?? It seems to extend the definition of of_translate_address. Thanks, Zhichang > > Arnd >

Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

me special I/O port operations were registered > for the port number, using an architecture specific > function that arm64 implements. Other architectures > like x86 that don't have a direct mapping between I/O > ports and MMIO addresses would implement that same > function differently. What about add the specific quirk for Hip06 LPC in of_empty_ranges_quirk()?? you know, there are several cases in which of_translate_address return OF_BAD_ADDR. And if we only check the special port range, it seems a bit risky. If some device want to use this port range when no hip06 LPC is configured, the checking does not work. I think we should also check the relevant device. Best, Zhichang > > Arnd >

Re: [PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

me special I/O port operations were registered > for the port number, using an architecture specific > function that arm64 implements. Other architectures > like x86 that don't have a direct mapping between I/O > ports and MMIO addresses would implement that same > function differently. What about add the specific quirk for Hip06 LPC in of_empty_ranges_quirk()?? you know, there are several cases in which of_translate_address return OF_BAD_ADDR. And if we only check the special port range, it seems a bit risky. If some device want to use this port range when no hip06 LPC is configured, the checking does not work. I think we should also check the relevant device. Best, Zhichang > > Arnd >

Re: [PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

gt; +#ifdef CONFIG_ARM64_INDIRECT_PIO >>>> +if (arm64_extio_ops && arm64_extio_ops->start <= addr && >>>> +addr <= arm64_extio_ops->end) >>>> +return extio_inb(addr); >>>> +#endif >>

Re: [PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

gt; +#ifdef CONFIG_ARM64_INDIRECT_PIO >>>> +if (arm64_extio_ops && arm64_extio_ops->start <= addr && >>>> +addr <= arm64_extio_ops->end) >>>> +return extio_inb(addr); >>>> +#endif >>

Re: [PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

#ifdef CONFIG_ARM64_INDIRECT_PIO >>>> +if (arm64_extio_ops && arm64_extio_ops->start <= addr && >>>> +addr <= arm64_extio_ops->end) >>>> +return extio_inb(addr); >>

Re: [PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

#ifdef CONFIG_ARM64_INDIRECT_PIO >>>> +if (arm64_extio_ops && arm64_extio_ops->start <= addr && >>>> +addr <= arm64_extio_ops->end) >>>> +return extio_inb(addr); >>

[PATCH V3 4/4] ARM64 LPC: support earlycon for UART connected to LPC

From: "zhichang.yuan" This patch support the earlycon for UART connected to LPC on Hip06. This patch is depended on the LPC driver. Signed-off-by: zhichang.yuan --- drivers/bus/hisi_lpc.c | 113

[PATCH V3 4/4] ARM64 LPC: support earlycon for UART connected to LPC

From: "zhichang.yuan" This patch support the earlycon for UART connected to LPC on Hip06. This patch is depended on the LPC driver. Signed-off-by: zhichang.yuan --- drivers/bus/hisi_lpc.c | 113 +++ drivers/tty/serial/8250/8250_early.c | 26

[PATCH V3 3/4] ARM64 LPC: support serial based on low-pin-count

_hisi_lpc.c b/drivers/tty/serial/8250/8250_hisi_lpc.c new file mode 100644 index 000..a8ba1ca --- /dev/null +++ b/drivers/tty/serial/8250/8250_hisi_lpc.c @@ -0,0 +1,171 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan <yuanzhich...@hisilicon.com> + * A

[PATCH V3 3/4] ARM64 LPC: support serial based on low-pin-count

<0x01 0x2f8 0x08>; + ret-names = "lpc_mem", "dev_io"; + status = "disabled"; + }; + }; diff --git a/drivers/tty/serial/8250/8250_hisi_lpc.c b/drivers/tty/serial/8250/8250_hisi_lpc.c new file mode 100644 in

[PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

+= mips_cdmm.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c new file mode 100644 index 000..9b364d0 --- /dev/null +++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,653 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights R

[PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

0644 index 000..1e7a9c5 --- /dev/null +++ b/drivers/bus/extio.c @@ -0,0 +1,66 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan <yuanzhich...@hisilicon.com> + * Author: Zou Rongrong <@huawei.com> + * + * This program is free software; you can

[PATCH V3 2/4] ARM64 LPC: LPC driver implementation on Hip06

bu-mbus.o diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c new file mode 100644 index 000..9b364d0 --- /dev/null +++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,653 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan + * Author: Zou Rongrong <

[PATCH V3 1/4] ARM64 LPC: Indirect ISA port IO introduced

fer, count); + else +#endif + writesb(PCI_IOBASE + addr, buffer, count); +} + + /* * String version of I/O memory access operations. */ diff --git a/drivers/bus/extio.c b/drivers/bus/extio.c new file mode 100644 index 000..1e7a9c5 --- /dev/null +++ b/drivers/bus/extio.c @@ -

[PATCH V3 0/4] ARM64 LPC: legacy ISA I/O support

PC driver in ISA compatible mode; - Reserve the IO range below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; Signed-off-by: Zhichang Yuan <yuanzhich...@hisilicon.com> zhichang.yuan (4): ARM64 LPC: Indirect ISA port IO intro

[PATCH V3 0/4] ARM64 LPC: legacy ISA I/O support

tible mode; - Reserve the IO range below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; Signed-off-by: Zhichang Yuan zhichang.yuan (4): ARM64 LPC: Indirect ISA port IO introduced ARM64 LPC: LPC driver implementation on Hip06 ARM64 LP

Re: [PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

On 2016年09月08日 19:04, Arnd Bergmann wrote: > On Thursday, September 8, 2016 6:04:31 PM CEST zhichang wrote: >> Hi, Arnd, >> >> On 2016年09月07日 22:52, Arnd Bergmann wrote: >>> On Wednesday, September 7, 2016 9:33:53 PM CEST Zhichang Yuan wrote: >>

Re: [PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

On 2016年09月08日 19:04, Arnd Bergmann wrote: > On Thursday, September 8, 2016 6:04:31 PM CEST zhichang wrote: >> Hi, Arnd, >> >> On 2016年09月07日 22:52, Arnd Bergmann wrote: >>> On Wednesday, September 7, 2016 9:33:53 PM CEST Zhichang Yuan wrote: >>>> F

Re: [PATCH V2 2/4] ARM64 LPC: LPC driver implementation on Hip06

n is supported. The early_in/early_out operation is defined in hisi_lpc.c too, we can directly call the hisilpc_target_in/hisilpc_target_out to finish the LPC IO operations. At this moment, all the IO functions specific to the child devices of hip06 LPC have their own indirect call method. This lpc_io_ops will be removed in V3. > > What are the other LPC cycle types that could be supported? O. memory and firmware operations are supported too. But at this moment, we only use IO cycle. Best, Zhichang > > Arnd >

Re: [PATCH V2 2/4] ARM64 LPC: LPC driver implementation on Hip06

n is supported. The early_in/early_out operation is defined in hisi_lpc.c too, we can directly call the hisilpc_target_in/hisilpc_target_out to finish the LPC IO operations. At this moment, all the IO functions specific to the child devices of hip06 LPC have their own indirect call method. This lpc_io_ops will be removed in V3. > > What are the other LPC cycle types that could be supported? O. memory and firmware operations are supported too. But at this moment, we only use IO cycle. Best, Zhichang > > Arnd >

Re: [PATCH V2 1/4] ARM64 LPC: Indirect ISA port IO introduced

Hi, Arnd, On 2016年09月08日 21:23, Arnd Bergmann wrote: > On Thursday, September 8, 2016 3:45:21 PM CEST zhichang.yuan wrote: >> On 2016/9/7 23:06, Arnd Bergmann wrote: >>> On Wednesday, September 7, 2016 9:33:50 PM CEST Zhichang Yuan wrote: >>>> +#i

Re: [PATCH V2 1/4] ARM64 LPC: Indirect ISA port IO introduced

Hi, Arnd, On 2016年09月08日 21:23, Arnd Bergmann wrote: > On Thursday, September 8, 2016 3:45:21 PM CEST zhichang.yuan wrote: >> On 2016/9/7 23:06, Arnd Bergmann wrote: >>> On Wednesday, September 7, 2016 9:33:50 PM CEST Zhichang Yuan wrote: >>>> +#i

Re: [PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

Hi, Arnd, On 2016年09月07日 22:52, Arnd Bergmann wrote: > On Wednesday, September 7, 2016 9:33:53 PM CEST Zhichang Yuan wrote: >> From: "zhichang.yuan" <yuanzhich...@hisilicon.com> >> >> This patch support the earlycon for UART connected to LPC on Hip06. >&g

Re: [PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

Hi, Arnd, On 2016年09月07日 22:52, Arnd Bergmann wrote: > On Wednesday, September 7, 2016 9:33:53 PM CEST Zhichang Yuan wrote: >> From: "zhichang.yuan" >> >> This patch support the earlycon for UART connected to LPC on Hip06. >> This patch is depende

Re: [PATCH V2 3/4] ARM64 LPC: support serial based on low-pin-count

Hi, Arnd On 2016年09月07日 22:50, Arnd Bergmann wrote: > On Wednesday, September 7, 2016 9:33:52 PM CEST Zhichang Yuan wrote: >> From: "zhichang.yuan" <yuanzhich...@hisilicon.com> >> >> On Hip06 platform, a 16550 compatible UART is connected to low-pin-count

Re: [PATCH V2 3/4] ARM64 LPC: support serial based on low-pin-count

Hi, Arnd On 2016年09月07日 22:50, Arnd Bergmann wrote: > On Wednesday, September 7, 2016 9:33:52 PM CEST Zhichang Yuan wrote: >> From: "zhichang.yuan" >> >> On Hip06 platform, a 16550 compatible UART is connected to low-pin-count and >> controlled through

[PATCH V2 0/4] ARM64 LPC: legacy ISA I/O support

compatible mode; - Reserve the IO range below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; Signed-off-by: Zhichang Yuan <yuanzhich...@hisilicon.com> zhichang.yuan (4): ARM64 LPC: Indirect ISA port IO introduced ARM64 LPC: LPC

[PATCH V2 2/4] ARM64 LPC: LPC driver implementation on Hip06

+++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,496 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan <yuanzhich...@hisilicon.com> + * Author: Zou Rongrong <@huawei.com> + * + * This program is free software; you can redistribute it and/or modify

[PATCH V2 0/4] ARM64 LPC: legacy ISA I/O support

e below 4K in avoid the possible conflict with PCI host IO ranges; - Support the LPC uart and relevant earlycon; Signed-off-by: Zhichang Yuan zhichang.yuan (4): ARM64 LPC: Indirect ISA port IO introduced ARM64 LPC: LPC driver implementation on Hip06 ARM64 LPC: support serial based

[PATCH V2 2/4] ARM64 LPC: LPC driver implementation on Hip06

= hisi_lpc.o obj-$(CONFIG_MIPS_CDMM)+= mips_cdmm.o obj-$(CONFIG_MVEBU_MBUS) += mvebu-mbus.o diff --git a/drivers/bus/hisi_lpc.c b/drivers/bus/hisi_lpc.c new file mode 100644 index 000..7ac0551 --- /dev/null +++ b/drivers/bus/hisi_lpc.c @@ -0,0 +1,496 @@ +/* + * Copyright

[PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

From: "zhichang.yuan" This patch support the earlycon for UART connected to LPC on Hip06. This patch is depended on the LPC driver. Signed-off-by: zhichang.yuan --- drivers/bus/hisi_lpc.c | 129

[PATCH V2 4/4] ARM64 LPC: support earlycon for UART connected to LPC

From: "zhichang.yuan" This patch support the earlycon for UART connected to LPC on Hip06. This patch is depended on the LPC driver. Signed-off-by: zhichang.yuan --- drivers/bus/hisi_lpc.c | 129 + 1 file changed, 129 insertions(+) diff --git

[PATCH V2 1/4] ARM64 LPC: Indirect ISA port IO introduced

From: "zhichang.yuan" For arm64, there is no I/O space as other architectural platforms, such as X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs, such as Hip06, when accessing some legacy ISA devices connected to LPC, those known port

[PATCH V2 1/4] ARM64 LPC: Indirect ISA port IO introduced

From: "zhichang.yuan" For arm64, there is no I/O space as other architectural platforms, such as X86. Most I/O accesses are achieved based on MMIO. But for some arm64 SoCs, such as Hip06, when accessing some legacy ISA devices connected to LPC, those known port addresses are explicitly used to

[PATCH V2 3/4] ARM64 LPC: support serial based on low-pin-count

50/8250_hisi_lpc.c b/drivers/tty/serial/8250/8250_hisi_lpc.c new file mode 100644 index 000..fbaae89 --- /dev/null +++ b/drivers/tty/serial/8250/8250_hisi_lpc.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan <yuanzhich...@hisi

[PATCH V2 3/4] ARM64 LPC: support serial based on low-pin-count

file mode 100644 index 000..fbaae89 --- /dev/null +++ b/drivers/tty/serial/8250/8250_hisi_lpc.c @@ -0,0 +1,104 @@ +/* + * Copyright (C) 2016 Hisilicon Limited, All Rights Reserved. + * Author: Zhichang Yuan + * Author: Zou Rongrong <@huawei.com> + * + * This program is free software; y

[PATCH v1] arm64:mm: enable the kernel execute attribute for HEAD_TEXT segment

ndary CPUs are booting based on spin-table mechanism, some functions in head.S are needed to run. Only PAGE_KERNEL dosen't work for this case. This patch will configure the page attributes as PAGE_KERNEL_EXEC for HEAD_TEXT segment. Signed-off-by: Zhichang Yuan --- arch/arm64/mm/

[PATCH v1] arm64:mm: enable the kernel execute attribute for HEAD_TEXT segment

the secondary CPUs are booting based on spin-table mechanism, some functions in head.S are needed to run. Only PAGE_KERNEL dosen't work for this case. This patch will configure the page attributes as PAGE_KERNEL_EXEC for HEAD_TEXT segment. Signed-off-by: Zhichang Yuan yuanzhich...@hisilicon.com

[PATCHv2] arm64:mm: free the useless initial page table

e is freed; Signed-off-by: Zhichang Yuan --- arch/arm64/include/asm/pgtable.h |3 +++ arch/arm64/mm/mmu.c | 15 --- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h index 41a43b

[PATCHv2] arm64:mm: free the useless initial page table

the unused page table is freed; Signed-off-by: Zhichang Yuan zhichang.y...@linaro.org --- arch/arm64/include/asm/pgtable.h |3 +++ arch/arm64/mm/mmu.c | 15 --- 2 files changed, 15 insertions(+), 3 deletions(-) diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64

[RFC PATCH v1] arm64:mm: An optimization about kernel direct sapce mapping

are mapped, then the second scanning will map the smaller memory ranges. Since the threshold is so small, in most cases, the second scanning is NULL operation. The patch is also accessible @ https://git.linaro.org/people/zhichang.yuan/pgalloc.git/shortlog/refs/heads/mapmem_linux_master Signed-off-by: Zhi

[RFC PATCH v1] arm64:mm: An optimization about kernel direct sapce mapping

-off-by: Zhichang Yuan zhichang.y...@linaro.org --- arch/arm64/include/asm/page.h| 10 ++ arch/arm64/include/asm/pgtable.h |3 + arch/arm64/kernel/vmlinux.lds.S |4 + arch/arm64/mm/mmu.c | 230 -- include/linux/memblock.h