Re: [Intel IOMMU][patch 4/8] Supporting Zero Length Reads in Intel IOMMU.

From: Andi Kleen <[EMAIL PROTECTED]> Date: Tue, 24 Apr 2007 21:28:11 +0200 > On Tuesday 24 April 2007 08:03:03 Ashok Raj wrote: > > PCI specs permit zero length reads (ZLR) even if the mapping for that > > region > > is write only. Support for this feature is indicated by the presence of a > >

Re: [Intel IOMMU][patch 4/8] Supporting Zero Length Reads in Intel IOMMU.

On Tue, Apr 24, 2007 at 09:28:11PM +0200, Andi Kleen wrote: > On Tuesday 24 April 2007 08:03:03 Ashok Raj wrote: > > PCI specs permit zero length reads (ZLR) even if the mapping for that > > region > > is write only. Support for this feature is indicated by the presence of a > > bit > > in the

Re: [Intel IOMMU][patch 4/8] Supporting Zero Length Reads in Intel IOMMU.

On Tuesday 24 April 2007 08:03:03 Ashok Raj wrote: > PCI specs permit zero length reads (ZLR) even if the mapping for that region > is write only. Support for this feature is indicated by the presence of a bit > in the DMAR capability. If a particular DMAR does not support this capability > we ma

[Intel IOMMU][patch 4/8] Supporting Zero Length Reads in Intel IOMMU.

PCI specs permit zero length reads (ZLR) even if the mapping for that region is write only. Support for this feature is indicated by the presence of a bit in the DMAR capability. If a particular DMAR does not support this capability we map write-only regions as read-write. This option can also p

[Intel IOMMU][patch 4/8] Supporting Zero Length Reads in Intel IOMMU.

PCI specs permit zero length reads (ZLR) even if the mapping for that region is write only. Support for this feature is indicated by the presence of a bit in the DMAR capability. If a particular DMAR does not support this capability we map write-only regions as read-write. This option can also p