Seems no issue now.
Thanks all.
On 2019-07-02 at 09:52:39 +0800, Li Wang wrote:
> On Tue, Jul 2, 2019 at 12:04 AM Ricardo Neri <
> ricardo.neri-calde...@linux.intel.com> wrote:
>
> > On Mon, Jul 01, 2019 at 08:57:28PM +0800, Li Wang wrote:
> > > On Mon, Jul 1, 2019 at 8:02 PM Paolo Bonzini
> >
On 01/07/19 16:53, Ricardo Neri wrote:
>>
>> (*) before the x86 people jump at me, this won't happen unless you
>> explicitly pass an option to QEMU, such as "-cpu host,+umip". :) The
>> incorrect emulation of SMSW when CR4.UMIP=1 is why.
> Paolo, what do you mean by the incorrect emulation of SMS
On Mon, Jul 01, 2019 at 08:57:28PM +0800, Li Wang wrote:
> On Mon, Jul 1, 2019 at 8:02 PM Paolo Bonzini wrote:
>
> > On 01/07/19 09:50, Li Wang wrote:
> > > Hello there,
> > >
> > > LTP/umip_basic_test get failed on KVM UMIP
> > > system(kernel-v5.2-rc4.x86_64). The test is only trying to do
> >
On Mon, Jul 01, 2019 at 02:02:35PM +0200, Paolo Bonzini wrote:
> On 01/07/19 09:50, Li Wang wrote:
> > Hello there,
> >
> > LTP/umip_basic_test get failed on KVM UMIP
> > system(kernel-v5.2-rc4.x86_64). The test is only trying to do
> > asm volatile("smsw %0\n" : "=m" (val));
> > and expect t
On 01/07/19 09:50, Li Wang wrote:
> Hello there,
>
> LTP/umip_basic_test get failed on KVM UMIP
> system(kernel-v5.2-rc4.x86_64). The test is only trying to do
> asm volatile("smsw %0\n" : "=m" (val));
> and expect to get SIGSEGV in this SMSW operation, but it exits with 0
> unexpectedly.
In
On Mon, 1 Jul 2019, Li Wang wrote:
> Hello there,
>
> LTP/umip_basic_test get failed on KVM UMIP system(kernel-v5.2-rc4.x86_64).
> The test is only trying to do
> asm volatile("smsw %0\n" : "=m" (val));
> and expect to get SIGSEGV in this SMSW operation, but it exits with 0
> unexpectedly.
>
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