Hi,
> >
> > + */
> > +static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool
> > +is_high) {
> > + struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master);
> > + u32 genfifoentry = 0x0, statusreg, timeout;
> > +
> > + genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
>
Hi,
+ */
+static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool
+is_high) {
+ struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi-master);
+ u32 genfifoentry = 0x0, statusreg, timeout;
+
+ genfifoentry |= GQSPI_GENFIFO_MODE_SPI;
+
hi,
Some minor comments.
On Fri, Jun 5, 2015 at 6:37 PM, Ranjit Waghmode
wrote:
> This patch adds support for GQSPI controller driver used by
> Zynq Ultrascale+ MPSoC
>
> Signed-off-by: Ranjit Waghmode
> ---
> Here is the v2 series.
> + */
> +static void zynqmp_qspi_chipselect(struct
hi,
Some minor comments.
On Fri, Jun 5, 2015 at 6:37 PM, Ranjit Waghmode
ranjit.waghm...@xilinx.com wrote:
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
Here is the v2 series.
snip
+ */
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode
---
Here is the v2 series.
Following comments are not taken care in this version:
a) Comment from Mark Brown regarding DMA manual mapping-
This QSPI DMA only supports RX and not
This patch adds support for GQSPI controller driver used by
Zynq Ultrascale+ MPSoC
Signed-off-by: Ranjit Waghmode ranjit.waghm...@xilinx.com
---
Here is the v2 series.
Following comments are not taken care in this version:
a) Comment from Mark Brown regarding DMA manual mapping-
This QSPI DMA
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