* Andi Kleen <[EMAIL PROTECTED]> wrote:
> After a lot of discussions with AMD it turns out that TSC on Fam10h
> CPUs is synchronized when the CONSTANT_TSC cpuid bit is set. Or rather
> that if there are ever systems where that is not true it would be
> their BIOS' task to disable the bit.
>
* Andi Kleen [EMAIL PROTECTED] wrote:
After a lot of discussions with AMD it turns out that TSC on Fam10h
CPUs is synchronized when the CONSTANT_TSC cpuid bit is set. Or rather
that if there are ever systems where that is not true it would be
their BIOS' task to disable the bit.
So
After a lot of discussions with AMD it turns out that TSC
on Fam10h CPUs is synchronized when the CONSTANT_TSC cpuid bit is set.
Or rather that if there are ever systems where that is not
true it would be their BIOS' task to disable the bit.
So finally use TSC gettimeofday on Fam10h by default.
After a lot of discussions with AMD it turns out that TSC
on Fam10h CPUs is synchronized when the CONSTANT_TSC cpuid bit is set.
Or rather that if there are ever systems where that is not
true it would be their BIOS' task to disable the bit.
So finally use TSC gettimeofday on Fam10h by default.
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