Re: [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h

* Andi Kleen <[EMAIL PROTECTED]> wrote: > The ACPI code currently disables TSC use in any C2 and C3 states. But > the AMD Fam10h BKDG documents that the TSC will never stop in any C > states when the CONSTANT_TSC bit is set. Make this disabling > conditional on CONSTANT_TSC not set on AMD. >

Re: [PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h

* Andi Kleen [EMAIL PROTECTED] wrote: The ACPI code currently disables TSC use in any C2 and C3 states. But the AMD Fam10h BKDG documents that the TSC will never stop in any C states when the CONSTANT_TSC bit is set. Make this disabling conditional on CONSTANT_TSC not set on AMD. I

[PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h

The ACPI code currently disables TSC use in any C2 and C3 states. But the AMD Fam10h BKDG documents that the TSC will never stop in any C states when the CONSTANT_TSC bit is set. Make this disabling conditional on CONSTANT_TSC not set on AMD. I actually think this is true on Intel too for C2

[PATCH] [18/20] x86: Don't disable TSC in any C states on AMD Fam10h

The ACPI code currently disables TSC use in any C2 and C3 states. But the AMD Fam10h BKDG documents that the TSC will never stop in any C states when the CONSTANT_TSC bit is set. Make this disabling conditional on CONSTANT_TSC not set on AMD. I actually think this is true on Intel too for C2