Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

xilinx.com> > > Cc: Arnd Bergmann <a...@arndb.de>; Greg Kroah-Hartman > > <gre...@linuxfoundation.org>; LKML <linux-kernel@vger.kernel.org>; > > michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval > > Rajeshbhai Shah <ds...@xilinx.com> > >

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

: Arnd Bergmann ; Greg Kroah-Hartman > > ; LKML ; > > michal.si...@xilinx.com; Hyun Kwon ; Dhaval > > Rajeshbhai Shah > > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > > logicoreIP init driver > > > > Daval, > > > > On Tue, Dec

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

undation.org>; LKML <linux-kernel@vger.kernel.org>; > michal.si...@xilinx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval > Rajeshbhai Shah <ds...@xilinx.com> > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > Daval, > >

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

bhai Shah > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > Daval, > > On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah > wrote: > > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > > cr

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Daval, On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. > >

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Daval, On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. > > Signed-off-by: Dhaval Shah [] >

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

.@xilinx.com> > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote: > > > Then you need to explain this a lot better, posting a random driver > > &g

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

nux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote: > > > Then you need to explain this a lot better, posting a random driver > > > for submission that is expected to be used by

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote: > > Then you need to explain this a lot better, posting a random driver for > > submission that is expected to be used by another one isn't ok. > > Post the whole patch series please, we do not add infrastructure to the > >

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Wed, Dec 06, 2017 at 09:05:51AM +, Dhaval Rajeshbhai Shah wrote: > > Then you need to explain this a lot better, posting a random driver for > > submission that is expected to be used by another one isn't ok. > > Post the whole patch series please, we do not add infrastructure to the > >

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

.@xilinx.com> > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote: > > Hi Greg k-h, > > > > Thanks a lot for the review. > > > > Replie

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

nux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote: > > Hi Greg k-h, > > > > Thanks a lot for the review. > > > > Replies inline. > > As they should be, perhaps

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote: > Hi Greg k-h, > > Thanks a lot for the review. > > Replies inline. As they should be, perhaps you need a better email client :) > > > +config XILINX_VCU > > + tristate "Xilinx VCU Init" > > + default n > >

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Wed, Dec 06, 2017 at 06:01:37AM +, Dhaval Rajeshbhai Shah wrote: > Hi Greg k-h, > > Thanks a lot for the review. > > Replies inline. As they should be, perhaps you need a better email client :) > > > +config XILINX_VCU > > + tristate "Xilinx VCU Init" > > + default n > >

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

nx.com; Hyun Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

; Dhaval Rajeshbhai Shah Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api whi

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Mailing List <linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun Kwon <hy...@xilinx.com> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 5, 2017 at 1:38 PM, Dhaval Rajeshbhai Shah <ds...@xil

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 5, 2017 at 1:38 PM, Dhaval Rajeshbhai Shah wrote: > From: arndbergm...@gmail.com [mailto:arndbergm...@gmail.com] On Behalf > Of Arnd Bergmann > Sent: Tuesday, December 05, 2017 4:19 AM > To: Dhava

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

om> > Cc: gregkh <gre...@linuxfoundation.org>; Linux Kernel Mailing List > <linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun > Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com> > Subject: Re: [PATCH] [linux][master][v1] misc:

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

ichal Simek ; Hyun > Kwon ; Dhaval Rajeshbhai Shah > Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU > logicoreIP init driver > > On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: >> Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design >&

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. Your subject has a lot of [] in it,

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Tue, Dec 05, 2017 at 03:43:32AM -0800, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. Your subject has a lot of [] in it,

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

ation.org>; Linux Kernel Mailing List <linux-kernel@vger.kernel.org>; Michal Simek <michal.si...@xilinx.com>; Hyun Kwon <hy...@xilinx.com>; Dhaval Rajeshbhai Shah <ds...@xilinx.com> Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init dri

RE: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

; Hyun Kwon ; Dhaval Rajeshbhai Shah Subject: Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide t

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. > > Signed-off-by:

Re: [PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

On Tue, Dec 5, 2017 at 12:43 PM, Dhaval Shah wrote: > Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design > created. This driver will provide the api which can be used > by the encoder and decoder driver to get the configured value. > > Signed-off-by: Dhaval Shah Can you explain

[PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design created. This driver will provide the api which can be used by the encoder and decoder driver to get the configured value. Signed-off-by: Dhaval Shah --- drivers/misc/Kconfig| 6 + drivers/misc/Makefile

[PATCH] [linux][master][v1] misc: Add Xilinx ZYNQMP VCU logicoreIP init driver

Xilinx ZYNQMP VCU Init driver is based on the new LogiCoreIP design created. This driver will provide the api which can be used by the encoder and decoder driver to get the configured value. Signed-off-by: Dhaval Shah --- drivers/misc/Kconfig| 6 + drivers/misc/Makefile | 1 +