>
> > In our specific case, a loadable driver will register to process
> > the NMI generated by a timer device on the IOAPIC pin. The driver
> > will need to unmask/mask the NMI interrupt at init/exit time.
> >
> > The timer NMI interrupt will be used to synchronize cluster nodes.
>
> We nor
> In our specific case, a loadable driver will register to process
> the NMI generated by a timer device on the IOAPIC pin. The driver
> will need to unmask/mask the NMI interrupt at init/exit time.
>
> The timer NMI interrupt will be used to synchronize cluster nodes.
We normally don't add h
>
> John Keller <[EMAIL PROTECTED]> writes:
>
> > Add support for IOAPIC NMI interrupts on x86_64.
> >
> > Changes include the following:
> >
> > - Obtain the NMI IOAPIC info via an ACPI NMI SRC structure that is
> > part of the MADT, and program the IOAPIC redirection register.
> > The N
John Keller <[EMAIL PROTECTED]> writes:
> Add support for IOAPIC NMI interrupts on x86_64.
>
> Changes include the following:
>
> - Obtain the NMI IOAPIC info via an ACPI NMI SRC structure that is
> part of the MADT, and program the IOAPIC redirection register.
> The NMI SRC struct wil
Add support for IOAPIC NMI interrupts on x86_64.
Changes include the following:
- Obtain the NMI IOAPIC info via an ACPI NMI SRC structure that is
part of the MADT, and program the IOAPIC redirection register.
The NMI SRC struct will contain the GSI of the NMI interrupt.
- Setup irq_
5 matches
Mail list logo