On Wed, Jul 26, 2017 at 9:16 AM, Liwei Song wrote:
> On 07/21/2017 05:56 PM, Andy Shevchenko wrote:
>> On Fri, Jul 21, 2017 at 12:41 PM, Song liwei
>> wrote:
>> /* Fixup common BIOS bug */
>> if (bit_offset == 0) {
>> if
On Wed, Jul 26, 2017 at 9:16 AM, Liwei Song wrote:
> On 07/21/2017 05:56 PM, Andy Shevchenko wrote:
>> On Fri, Jul 21, 2017 at 12:41 PM, Song liwei
>> wrote:
>> /* Fixup common BIOS bug */
>> if (bit_offset == 0) {
>> if (bit_width == 16 && (*paddr & 0x01) == 0 &&
On 07/21/2017 05:56 PM, Andy Shevchenko wrote:
> On Fri, Jul 21, 2017 at 12:41 PM, Song liwei wrote:
>
>> [Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
>>
>> This is due to an 8-bit access width is specified for a 16-bit register,
>> Do
On 07/21/2017 05:56 PM, Andy Shevchenko wrote:
> On Fri, Jul 21, 2017 at 12:41 PM, Song liwei wrote:
>
>> [Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
>>
>> This is due to an 8-bit access width is specified for a 16-bit register,
>> Do bit_width check just like what
On Fri, Jul 21, 2017 at 12:41 PM, Song liwei wrote:
> [Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
>
> This is due to an 8-bit access width is specified for a 16-bit register,
> Do bit_width check just like what the original commit have done.
On Fri, Jul 21, 2017 at 12:41 PM, Song liwei wrote:
> [Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
>
> This is due to an 8-bit access width is specified for a 16-bit register,
> Do bit_width check just like what the original commit have done.
> else if
From: Liwei Song
This is a follow up to commit f712c71f7b2b ("ACPI, APEI: Fixup common
access width firmware bug") fix the following firmware bug:
[Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
This is due to an 8-bit access width is specified
From: Liwei Song
This is a follow up to commit f712c71f7b2b ("ACPI, APEI: Fixup common
access width firmware bug") fix the following firmware bug:
[Firmware Bug]: APEI: Invalid bit width + offset in GAR [0xb2/16/0/1/1]
This is due to an 8-bit access width is specified for a 16-bit register,
Do
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