On 13/09/18 12:53, Brice Goglin wrote:
> Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
>>> On 13/09/18 06:51, Brice Goglin wrote:
[...]
By the way, did anybody actually see an error with lstopo when there's
no "type" attribute for L3? I can't reproduce any issue, we just skip
On 13/09/18 12:53, Brice Goglin wrote:
> Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
>>> On 13/09/18 06:51, Brice Goglin wrote:
[...]
By the way, did anybody actually see an error with lstopo when there's
no "type" attribute for L3? I can't reproduce any issue, we just skip
On 9/13/2018 5:53 AM, Brice Goglin wrote:
Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
Hi Brice,
On 13/09/18 06:51, Brice Goglin wrote:
Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
Yes. Without this change, we hit the lscpu
On 9/13/2018 5:53 AM, Brice Goglin wrote:
Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
Hi Brice,
On 13/09/18 06:51, Brice Goglin wrote:
Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
Yes. Without this change, we hit the lscpu
Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
> On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
>> Hi Brice,
>>
>> On 13/09/18 06:51, Brice Goglin wrote:
>>> Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
> Yes. Without this change, we hit the lscpu error in the commit message,
Le 13/09/2018 à 11:35, Sudeep Holla a écrit :
> On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
>> Hi Brice,
>>
>> On 13/09/18 06:51, Brice Goglin wrote:
>>> Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
> Yes. Without this change, we hit the lscpu error in the commit message,
On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
> Hi Brice,
>
> On 13/09/18 06:51, Brice Goglin wrote:
> > Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
> >>> Yes. Without this change, we hit the lscpu error in the commit message,
> >>> and get zero output about the system. We don't
On Thu, Sep 13, 2018 at 10:39:10AM +0100, James Morse wrote:
> Hi Brice,
>
> On 13/09/18 06:51, Brice Goglin wrote:
> > Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
> >>> Yes. Without this change, we hit the lscpu error in the commit message,
> >>> and get zero output about the system. We don't
Hi Brice,
On 13/09/18 06:51, Brice Goglin wrote:
> Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
>>> Yes. Without this change, we hit the lscpu error in the commit message,
>>> and get zero output about the system. We don't even get information
>>> about the caches which are architecturally
Hi Brice,
On 13/09/18 06:51, Brice Goglin wrote:
> Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
>>> Yes. Without this change, we hit the lscpu error in the commit message,
>>> and get zero output about the system. We don't even get information
>>> about the caches which are architecturally
Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
>
>> Yes. Without this change, we hit the lscpu error in the commit message,
>> and get zero output about the system. We don't even get information
>> about the caches which are architecturally specified or how many cpus
>> are present. With this
Le 12/09/2018 à 11:49, Sudeep Holla a écrit :
>
>> Yes. Without this change, we hit the lscpu error in the commit message,
>> and get zero output about the system. We don't even get information
>> about the caches which are architecturally specified or how many cpus
>> are present. With this
On 9/12/2018 10:15 AM, Sudeep Holla wrote:
On Wed, Sep 12, 2018 at 09:57:14AM -0600, Jeffrey Hugo wrote:
On 9/12/2018 9:38 AM, Sudeep Holla wrote:
On 12/09/18 16:27, Sudeep Holla wrote:
On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
Correct. However, what if you have a NOCACHE (not
On 9/12/2018 10:15 AM, Sudeep Holla wrote:
On Wed, Sep 12, 2018 at 09:57:14AM -0600, Jeffrey Hugo wrote:
On 9/12/2018 9:38 AM, Sudeep Holla wrote:
On 12/09/18 16:27, Sudeep Holla wrote:
On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
Correct. However, what if you have a NOCACHE (not
On Wed, Sep 12, 2018 at 09:57:14AM -0600, Jeffrey Hugo wrote:
> On 9/12/2018 9:38 AM, Sudeep Holla wrote:
> >
> >
> >On 12/09/18 16:27, Sudeep Holla wrote:
> >>
> >>
> >>On 12/09/18 15:41, Jeffrey Hugo wrote:
> >
> >[...]
> >
> >>>
> >>>Correct. However, what if you have a NOCACHE (not
On Wed, Sep 12, 2018 at 09:57:14AM -0600, Jeffrey Hugo wrote:
> On 9/12/2018 9:38 AM, Sudeep Holla wrote:
> >
> >
> >On 12/09/18 16:27, Sudeep Holla wrote:
> >>
> >>
> >>On 12/09/18 15:41, Jeffrey Hugo wrote:
> >
> >[...]
> >
> >>>
> >>>Correct. However, what if you have a NOCACHE (not
On 9/12/2018 9:39 AM, Jeremy Linton wrote:
Hi,
On 09/12/2018 09:41 AM, Jeffrey Hugo wrote:
The HW designers have indicated that there is no sane way to provide
sets/ways information to software, even on an informational basis (ie
not for cache maintenance, but for performance optimizations).
On 9/12/2018 9:39 AM, Jeremy Linton wrote:
Hi,
On 09/12/2018 09:41 AM, Jeffrey Hugo wrote:
The HW designers have indicated that there is no sane way to provide
sets/ways information to software, even on an informational basis (ie
not for cache maintenance, but for performance optimizations).
On 9/12/2018 9:38 AM, Sudeep Holla wrote:
On 12/09/18 16:27, Sudeep Holla wrote:
On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
Correct. However, what if you have a NOCACHE (not architecturally
specified), that is fully described in PPTT, as a non-unified cache
(data only)? Unlikely?
On 9/12/2018 9:38 AM, Sudeep Holla wrote:
On 12/09/18 16:27, Sudeep Holla wrote:
On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
Correct. However, what if you have a NOCACHE (not architecturally
specified), that is fully described in PPTT, as a non-unified cache
(data only)? Unlikely?
Hi,
On 09/12/2018 09:41 AM, Jeffrey Hugo wrote:
The HW designers have indicated that there is no sane way to provide
sets/ways information to software, even on an informational basis (ie
not for cache maintenance, but for performance optimizations). Therefore
the firmware will not provide
Hi,
On 09/12/2018 09:41 AM, Jeffrey Hugo wrote:
The HW designers have indicated that there is no sane way to provide
sets/ways information to software, even on an informational basis (ie
not for cache maintenance, but for performance optimizations). Therefore
the firmware will not provide
On 12/09/18 16:27, Sudeep Holla wrote:
>
>
> On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
>>
>> Correct. However, what if you have a NOCACHE (not architecturally
>> specified), that is fully described in PPTT, as a non-unified cache
>> (data only)? Unlikely? Maybe. Still seem possible
On 12/09/18 16:27, Sudeep Holla wrote:
>
>
> On 12/09/18 15:41, Jeffrey Hugo wrote:
[...]
>>
>> Correct. However, what if you have a NOCACHE (not architecturally
>> specified), that is fully described in PPTT, as a non-unified cache
>> (data only)? Unlikely? Maybe. Still seem possible
On 12/09/18 15:48, Jeffrey Hugo wrote:
> On 9/12/2018 4:49 AM, Sudeep Holla wrote:
>>
>>
>> On 11/09/18 21:38, Jeffrey Hugo wrote:
>>> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
>>
>> [..]
>>
If you look at the next line of code following this
On 12/09/18 15:48, Jeffrey Hugo wrote:
> On 9/12/2018 4:49 AM, Sudeep Holla wrote:
>>
>>
>> On 11/09/18 21:38, Jeffrey Hugo wrote:
>>> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
>>
>> [..]
>>
If you look at the next line of code following this
On 12/09/18 15:41, Jeffrey Hugo wrote:
> On 9/11/2018 3:25 PM, Jeremy Linton wrote:
>> Hi,
>>
>> On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
>>> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
> The type
On 12/09/18 15:41, Jeffrey Hugo wrote:
> On 9/11/2018 3:25 PM, Jeremy Linton wrote:
>> Hi,
>>
>> On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
>>> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
> The type
On 9/12/2018 4:49 AM, Sudeep Holla wrote:
On 11/09/18 21:38, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
[..]
If you look at the next line of code following this comment its going
to update the cache type for fully populated PPTT nodes.
On 9/12/2018 4:49 AM, Sudeep Holla wrote:
On 11/09/18 21:38, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
[..]
If you look at the next line of code following this comment its going
to update the cache type for fully populated PPTT nodes.
On 9/11/2018 3:25 PM, Jeremy Linton wrote:
Hi,
On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural
mechanisms (ie
system
On 9/11/2018 3:25 PM, Jeremy Linton wrote:
Hi,
On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural
mechanisms (ie
system
On 11/09/18 21:38, Jeffrey Hugo wrote:
> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
>> Hi Jeffrey,
>>
>> (+Sudeep)
>>
[..]
>>
>> If you look at the next line of code following this comment its going
>> to update the cache type for fully populated PPTT nodes. Although with
>> the suggested
On 11/09/18 21:38, Jeffrey Hugo wrote:
> On 9/11/2018 2:16 PM, Jeremy Linton wrote:
>> Hi Jeffrey,
>>
>> (+Sudeep)
>>
[..]
>>
>> If you look at the next line of code following this comment its going
>> to update the cache type for fully populated PPTT nodes. Although with
>> the suggested
On 11/09/18 21:16, Jeremy Linton wrote:
> Hi Jeffrey,
>
> (+Sudeep)
>
Thanks for looping me in.
>
> If you look at the next line of code following this comment its going to
> update the cache type for fully populated PPTT nodes. Although with the
> suggested change its only going to
On 11/09/18 21:16, Jeremy Linton wrote:
> Hi Jeffrey,
>
> (+Sudeep)
>
Thanks for looping me in.
>
> If you look at the next line of code following this comment its going to
> update the cache type for fully populated PPTT nodes. Although with the
> suggested change its only going to
Hi,
On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural
mechanisms (ie
system registers), but its type might be specified in the
Hi,
On 09/11/2018 03:38 PM, Jeffrey Hugo wrote:
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural
mechanisms (ie
system registers), but its type might be specified in the
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural mechanisms
(ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT
On 9/11/2018 2:16 PM, Jeremy Linton wrote:
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural mechanisms
(ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural mechanisms (ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT specification, we should identify the cache as
the type
Hi Jeffrey,
(+Sudeep)
On 09/11/2018 02:32 PM, Jeffrey Hugo wrote:
The type of a cache might not be specified by architectural mechanisms (ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT specification, we should identify the cache as
the type
The type of a cache might not be specified by architectural mechanisms (ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT specification, we should identify the cache as
the type specified by PPTT.
This fixes the following lscpu issue where only
The type of a cache might not be specified by architectural mechanisms (ie
system registers), but its type might be specified in the PPTT. In this
case, following the PPTT specification, we should identify the cache as
the type specified by PPTT.
This fixes the following lscpu issue where only
44 matches
Mail list logo
