Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-07 Thread Borislav Petkov
On Tue, Jan 21, 2014 at 03:03:36PM -0600, Aravind Gopalakrishnan wrote: > The current logic that returns (sys_addr >> 8) & 0x7 when > num_dcts_intlv = 4 is incorrect. We should really be doing- > If intlv_addr = 0x4, then interleave on bits [9:8] and if > intlv_addr = 0x5, interleave on bits

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-07 Thread Borislav Petkov
On Tue, Jan 21, 2014 at 03:03:36PM -0600, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr 8) 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9].

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Aravind Gopalakrishnan
On 2/3/2014 1:32 PM, Borislav Petkov wrote: On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote: On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr >> 8) & 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Borislav Petkov
On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote: > On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: > >The current logic that returns (sys_addr >> 8) & 0x7 when > >num_dcts_intlv = 4 is incorrect. We should really be doing- > >If intlv_addr = 0x4, then interleave on bits

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Aravind Gopalakrishnan
On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr >> 8) & 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9]. Refer F15 M30h BKDG

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Aravind Gopalakrishnan
On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr 8) 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9]. Refer F15 M30h BKDG

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Borislav Petkov
On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote: On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr 8) 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and

Re: [PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-02-03 Thread Aravind Gopalakrishnan
On 2/3/2014 1:32 PM, Borislav Petkov wrote: On Mon, Feb 03, 2014 at 01:10:42PM -0600, Aravind Gopalakrishnan wrote: On 1/21/2014 3:03 PM, Aravind Gopalakrishnan wrote: The current logic that returns (sys_addr 8) 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If

[PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-01-21 Thread Aravind Gopalakrishnan
The current logic that returns (sys_addr >> 8) & 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9]. Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)

[PATCH] AMD64_EDAC: Fix logic to determine channel for F15 M30h processors

2014-01-21 Thread Aravind Gopalakrishnan
The current logic that returns (sys_addr 8) 0x7 when num_dcts_intlv = 4 is incorrect. We should really be doing- If intlv_addr = 0x4, then interleave on bits [9:8] and if intlv_addr = 0x5, interleave on bits [10:9]. Refer F15 M30h BKDG D18F2x110[7:6] (DRAM Controller Select Low)