Re: [PATCH] ARM: aspeed: g5: Do not set sirq polarity

2020-09-09 Thread Joel Stanley
On Thu, 27 Aug 2020 at 06:27, Jeremy Kerr wrote: > > Hi Joel, > > > A feature was added to the aspeed vuart driver to configure the vuart > > interrupt (sirq) polarity according to the LPC/eSPI strapping register. > > > > Systems that depend on a active low behaviour (sirq_polarity set to 0) > > s

Re: [PATCH] ARM: aspeed: g5: Do not set sirq polarity

2020-08-26 Thread Jeremy Kerr
Hi Joel, > A feature was added to the aspeed vuart driver to configure the vuart > interrupt (sirq) polarity according to the LPC/eSPI strapping register. > > Systems that depend on a active low behaviour (sirq_polarity set to 0) > such as OpenPower boxes also use LPC, so this relationship does n

[PATCH] ARM: aspeed: g5: Do not set sirq polarity

2020-08-12 Thread Joel Stanley
A feature was added to the aspeed vuart driver to configure the vuart interrupt (sirq) polarity according to the LPC/eSPI strapping register. Systems that depend on a active low behaviour (sirq_polarity set to 0) such as OpenPower boxes also use LPC, so this relationship does not hold. The proper