Lee Jones writes:
> On Tue, 05 May 2015, Eric Anholt wrote:
>
>> Stephen Warren writes:
>>
>> > On 05/04/2015 01:33 PM, Eric Anholt wrote:
>> >> There exists a tiny MMU, configurable only by the VC (running the
>> >> closed firmware), which maps from the ARM's physical addresses to bus
>> >>
On Tue, 05 May 2015, Eric Anholt wrote:
> Stephen Warren writes:
>
> > On 05/04/2015 01:33 PM, Eric Anholt wrote:
> >> There exists a tiny MMU, configurable only by the VC (running the
> >> closed firmware), which maps from the ARM's physical addresses to bus
> >> addresses. These bus
On Tue, 05 May 2015, Eric Anholt wrote:
Stephen Warren swar...@wwwdotorg.org writes:
On 05/04/2015 01:33 PM, Eric Anholt wrote:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus
Lee Jones l...@kernel.org writes:
On Tue, 05 May 2015, Eric Anholt wrote:
Stephen Warren swar...@wwwdotorg.org writes:
On 05/04/2015 01:33 PM, Eric Anholt wrote:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical
Stephen Warren writes:
> On 05/04/2015 01:33 PM, Eric Anholt wrote:
>> There exists a tiny MMU, configurable only by the VC (running the
>> closed firmware), which maps from the ARM's physical addresses to bus
>> addresses. These bus addresses determine the caching behavior in the
>> VC's L1/L2
On 05/04/2015 02:25 PM, Noralf Trønnes wrote:
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
On 05/04/2015 01:33 PM, Eric Anholt wrote:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's
Den 05.05.2015 02:07, skrev Eric Anholt:
Noralf Trønnes writes:
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the
Den 05.05.2015 02:07, skrev Eric Anholt:
Noralf Trønnes nor...@tronnes.org writes:
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses
On 05/04/2015 01:33 PM, Eric Anholt wrote:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's
On 05/04/2015 02:25 PM, Noralf Trønnes wrote:
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
Stephen Warren swar...@wwwdotorg.org writes:
On 05/04/2015 01:33 PM, Eric Anholt wrote:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
Noralf Trønnes writes:
> Den 04.05.2015 21:33, skrev Eric Anholt:
>> There exists a tiny MMU, configurable only by the VC (running the
>> closed firmware), which maps from the ARM's physical addresses to bus
>> addresses. These bus addresses determine the caching behavior in the
>> VC's L1/L2
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2)
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in
Noralf Trønnes nor...@tronnes.org writes:
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
Den 04.05.2015 21:33, skrev Eric Anholt:
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2)
There exists a tiny MMU, configurable only by the VC (running the
closed firmware), which maps from the ARM's physical addresses to bus
addresses. These bus addresses determine the caching behavior in the
VC's L1/L2 (note: separate from the ARM's L1/L2) according to the top
2 bits. The bits in
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