[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Masahiro Yamada
2016-04-26 16:52 GMT+09:00 Arnd Bergmann : > On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote: >> Hi Arnd, >> >> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : >> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: >> >> This outer cache allows to control

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Masahiro Yamada
2016-04-26 16:52 GMT+09:00 Arnd Bergmann : > On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote: >> Hi Arnd, >> >> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : >> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: >> >> This outer cache allows to control active ways independently for >>

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Arnd Bergmann
On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote: > Hi Arnd, > > 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : > > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > >> This outer cache allows to control active ways independently for > >> each CPU, but currently nothing

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-26 Thread Arnd Bergmann
On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote: > Hi Arnd, > > 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : > > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > >> This outer cache allows to control active ways independently for > >> each CPU, but currently nothing is done for

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-25 Thread Masahiro Yamada
Hi Arnd, 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: >> This outer cache allows to control active ways independently for >> each CPU, but currently nothing is done for secondary CPUs. In >> other words, all the ways are

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-25 Thread Masahiro Yamada
Hi Arnd, 2016-04-26 7:13 GMT+09:00 Arnd Bergmann : > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: >> This outer cache allows to control active ways independently for >> each CPU, but currently nothing is done for secondary CPUs. In >> other words, all the ways are locked for secondary

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-25 Thread Arnd Bergmann
On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > This outer cache allows to control active ways independently for > each CPU, but currently nothing is done for secondary CPUs. In > other words, all the ways are locked for secondary CPUs by default. > This commit fixes it to fully bring

Re: [PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-25 Thread Arnd Bergmann
On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote: > This outer cache allows to control active ways independently for > each CPU, but currently nothing is done for secondary CPUs. In > other words, all the ways are locked for secondary CPUs by default. > This commit fixes it to fully bring

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-20 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-20 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-20 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-20 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-15 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two

[PATCH] ARM: cache-uniphier: activate ways for secondary CPUs

2016-04-15 Thread Masahiro Yamada
This outer cache allows to control active ways independently for each CPU, but currently nothing is done for secondary CPUs. In other words, all the ways are locked for secondary CPUs by default. This commit fixes it to fully bring out the performance of this outer cache. There would be two