This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
2016-04-26 16:52 GMT+09:00 Arnd Bergmann :
> On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
>> Hi Arnd,
>>
>> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
>> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> >> This outer cache allows to control
2016-04-26 16:52 GMT+09:00 Arnd Bergmann :
> On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
>> Hi Arnd,
>>
>> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
>> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> >> This outer cache allows to control active ways independently for
>>
On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
> Hi Arnd,
>
> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> >> This outer cache allows to control active ways independently for
> >> each CPU, but currently nothing
On Tuesday 26 April 2016 09:55:35 Masahiro Yamada wrote:
> Hi Arnd,
>
> 2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
> > On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> >> This outer cache allows to control active ways independently for
> >> each CPU, but currently nothing is done for
Hi Arnd,
2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
> On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> This outer cache allows to control active ways independently for
>> each CPU, but currently nothing is done for secondary CPUs. In
>> other words, all the ways are
Hi Arnd,
2016-04-26 7:13 GMT+09:00 Arnd Bergmann :
> On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
>> This outer cache allows to control active ways independently for
>> each CPU, but currently nothing is done for secondary CPUs. In
>> other words, all the ways are locked for secondary
On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> This outer cache allows to control active ways independently for
> each CPU, but currently nothing is done for secondary CPUs. In
> other words, all the ways are locked for secondary CPUs by default.
> This commit fixes it to fully bring
On Friday 15 April 2016 16:05:46 Masahiro Yamada wrote:
> This outer cache allows to control active ways independently for
> each CPU, but currently nothing is done for secondary CPUs. In
> other words, all the ways are locked for secondary CPUs by default.
> This commit fixes it to fully bring
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
This outer cache allows to control active ways independently for
each CPU, but currently nothing is done for secondary CPUs. In
other words, all the ways are locked for secondary CPUs by default.
This commit fixes it to fully bring out the performance of this
outer cache.
There would be two
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