On 20/11/2018 21:40:49+0100, Alexandre Belloni wrote:
> On 20/11/2018 19:01:32+0100, Romain Izard wrote:
> > Le mar. 20 nov. 2018 à 18:16, Alexandre Belloni
> > a écrit :
> > >
> > > Hello Romain,
> > >
> > > On 20/11/2018 17:57:37+0100, Romain Izard wrote:
> > > > The SAMA5D2 is different from SA
On 20/11/2018 19:01:32+0100, Romain Izard wrote:
> Le mar. 20 nov. 2018 à 18:16, Alexandre Belloni
> a écrit :
> >
> > Hello Romain,
> >
> > On 20/11/2018 17:57:37+0100, Romain Izard wrote:
> > > The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
> > > different clocks for the per
Le mar. 20 nov. 2018 à 18:16, Alexandre Belloni
a écrit :
>
> Hello Romain,
>
> On 20/11/2018 17:57:37+0100, Romain Izard wrote:
> > The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
> > different clocks for the peripherals in the SoC. The Static Memory
> > controller is connecte
Hello Romain,
On 20/11/2018 17:57:37+0100, Romain Izard wrote:
> The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
> different clocks for the peripherals in the SoC. The Static Memory
> controller is connected to the divided master clock.
>
> Unfortunately, the device tree does
The SAMA5D2 is different from SAMA5D3 and SAMA5D4, as there are two
different clocks for the peripherals in the SoC. The Static Memory
controller is connected to the divided master clock.
Unfortunately, the device tree does not correctly show this and uses the
master clock directly. This clock is
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