On Mon, Mar 06, 2017 at 06:49:43PM +0900, Brian Kim wrote:
> On 2017년 03월 06일 16:24, Krzysztof Kozlowski wrote:
> > On Mon, Mar 6, 2017 at 4:52 AM, Brian Kim wrote:
> >> The power button on Odroid XU3/4 is connected with the PWRON pin of
> >> s2mps11 PMIC. The s2mps11 sends low signal to GPIO inpu
On 2017년 03월 06일 16:24, Krzysztof Kozlowski wrote:
> On Mon, Mar 6, 2017 at 4:52 AM, Brian Kim wrote:
>> The power button on Odroid XU3/4 is connected with the PWRON pin of
>> s2mps11 PMIC. The s2mps11 sends low signal to GPIO input in exynos 5422
>> via ONOB pin.
>>
>> This patch adds devicetree
On Mon, Mar 6, 2017 at 4:52 AM, Brian Kim wrote:
> The power button on Odroid XU3/4 is connected with the PWRON pin of
> s2mps11 PMIC. The s2mps11 sends low signal to GPIO input in exynos 5422
> via ONOB pin.
>
> This patch adds devicetree bindings for the power button of Odroid
> XU3/4.
>
> Signe
The power button on Odroid XU3/4 is connected with the PWRON pin of
s2mps11 PMIC. The s2mps11 sends low signal to GPIO input in exynos 5422
via ONOB pin.
This patch adds devicetree bindings for the power button of Odroid
XU3/4.
Signed-off-by: Brian Kim
---
arch/arm/boot/dts/exynos5422-odroidxu3
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