Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-06 Thread Daniel Schultz
Hi, On 03/05/2018 10:08 PM, Heiko Stübner wrote: Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner: Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Heiko Stübner
Am Montag, 5. März 2018, 21:25:30 CET schrieb Heiko Stübner: > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > > > Signed-off-

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Heiko Stübner
Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz applied for 4.17 Thanks Heiko

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Heiko Stübner
Hi Daniel, Am Montag, 5. März 2018, 16:57:13 CET schrieb Daniel Schultz: > On 03/05/2018 03:15 PM, Heiko Stuebner wrote: > > Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > >> The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > >> Set CLK_O_SEL to channel A t

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Daniel Schultz
Hi, On 03/05/2018 03:15 PM, Heiko Stuebner wrote: Hi Daniel, Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: Daniel S

Re: [PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Heiko Stuebner
Hi Daniel, Am Montag, 5. März 2018, 13:45:11 CET schrieb Daniel Schultz: > The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. > Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. > > Signed-off-by: Daniel Schultz > --- > > The binding will be added wi

[PATCH] ARM: dts: rockchip: Add dp83867 CLK_OUT muxing

2018-03-05 Thread Daniel Schultz
The CLK_O_SEL default is synchronous to XI input clock, which is 25 MHz. Set CLK_O_SEL to channel A transmit clock so we have 125 MHz on CLK_OUT. Signed-off-by: Daniel Schultz --- The binding will be added with the next merge of net-next: https://git.kernel.org/pub/scm/linux/kernel/git/davem/net