Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

Hi Huang, [auto build test ERROR on mvebu/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Caesar-Wang/ARM-errata-Workaround-for-Cortex-A12-erratum-818325/20151103-163417 config:

Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

在 2015年11月03日 16:45, Arnd Bergmann 写道: On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote: + /* Cortex-A12 Errata */ + ldr r10, =0x0c0d@ Cortex-A12 primary part number + teq r0, r10 + bne 5f beq __ca15_errata: +#ifdef

Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote: > > + /* Cortex-A12 Errata */ > + ldr r10, =0x0c0d@ Cortex-A12 primary part > number > + teq r0, r10 > + bne 5f > +#ifdef CONFIG_ARM_ERRATA_818325 > + teq r6, #0x00

[RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM

[RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an

Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

在 2015年11月03日 16:45, Arnd Bergmann 写道: On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote: + /* Cortex-A12 Errata */ + ldr r10, =0x0c0d@ Cortex-A12 primary part number + teq r0, r10 + bne 5f beq __ca15_errata: +#ifdef

Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Tuesday 03 November 2015 16:10:09 Caesar Wang wrote: > > + /* Cortex-A12 Errata */ > + ldr r10, =0x0c0d@ Cortex-A12 primary part > number > + teq r0, r10 > + bne 5f > +#ifdef CONFIG_ARM_ERRATA_818325 > + teq r6, #0x00

Re: [RESEND PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

Hi Huang, [auto build test ERROR on mvebu/for-next -- if it's inappropriate base, please suggest rules for selecting the more suitable base] url: https://github.com/0day-ci/linux/commits/Caesar-Wang/ARM-errata-Workaround-for-Cortex-A12-erratum-818325/20151103-163417 config:

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Tue, Aug 26, 2014 at 11:14:14AM +0100, Will Deacon wrote: > On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote: > > From: Huang Tao > > > > On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of > > two conditional store instructions with opposite condition code and

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote: > From: Huang Tao > > On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of > two conditional store instructions with opposite condition code and > updating the same register, the system might enter a deadlock if the

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

Hi Russell, I'd value your feedback on this if you have a moment. I think this will need by rk3288 soc. Thanks On 08/18/2014 05:58 PM, Kever Yang wrote: From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

Hi Russell, I'd value your feedback on this if you have a moment. I think this will need by rk3288 soc. Thanks On 08/18/2014 05:58 PM, Kever Yang wrote: From: Huang Tao huang...@rock-chips.com On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote: From: Huang Tao huang...@rock-chips.com On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter

Re: [PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

On Tue, Aug 26, 2014 at 11:14:14AM +0100, Will Deacon wrote: On Mon, Aug 18, 2014 at 10:58:09AM +0100, Kever Yang wrote: From: Huang Tao huang...@rock-chips.com On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite

[PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

From: Huang Tao On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an UNPREDICTABLE STR or STM

[PATCH] ARM: errata: Workaround for Cortex-A12 erratum 818325

From: Huang Tao huang...@rock-chips.com On Cortex-A12 (r0p0..r0p1-00lac0-rc11), when a CPU executes a sequence of two conditional store instructions with opposite condition code and updating the same register, the system might enter a deadlock if the second conditional instruction is an