On Fri, May 03, 2013 at 07:37:36AM +0200, Marek Belisko wrote:
> According documentation bit ACLKRPOL is set to 0 (receiver samples data
> on falling edge) and when set to 1 (receiver samples data on rising edge).
Applied, thanks.
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According documentation bit ACLKRPOL is set to 0 (receiver samples data
on falling edge) and when set to 1 (receiver samples data on rising edge).
I2S data are always sampled on falling edge and valid during rising edge
of bit clock. So in case of capture data transmitter sample data on falling
ed
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