Re: [PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips

2021-03-23 Thread Mark Brown
On Fri, 19 Mar 2021 18:48:46 +0800, Shengjiu Wang wrote: > The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz > and sample rate is 44100Hz, with the configuration pllprescale=2, > postscale=sysclkdiv=1, some chip may have wrong bclk > and lrclk output with pll enabled in master mo

Re: [PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips

2021-03-23 Thread Charles Keepax
On Fri, Mar 19, 2021 at 06:48:46PM +0800, Shengjiu Wang wrote: > The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz > and sample rate is 44100Hz, with the configuration pllprescale=2, > postscale=sysclkdiv=1, some chip may have wrong bclk > and lrclk output with pll enabled in mas

[PATCH] ASoC: wm8960: Fix wrong bclk and lrclk with pll enabled for some chips

2021-03-19 Thread Shengjiu Wang
The input MCLK is 12.288MHz, the desired output sysclk is 11.2896MHz and sample rate is 44100Hz, with the configuration pllprescale=2, postscale=sysclkdiv=1, some chip may have wrong bclk and lrclk output with pll enabled in master mode, but with the configuration pllprescale=1, postscale=2, the ou