> Engineering questions I need to bounce back to Marvell:
> * do I need to worry about PIO/UDMA timing? I don't see any registers
> or other knobs dealing with timing. Maybe the controller snoops?
In non-AHCI mode it certainly seems to do the snooping for you
Acked-by: Alan Cox <[EMAIL
Engineering questions I need to bounce back to Marvell:
* do I need to worry about PIO/UDMA timing? I don't see any registers
or other knobs dealing with timing. Maybe the controller snoops?
In non-AHCI mode it certainly seems to do the snooping for you
Acked-by: Alan Cox [EMAIL
Here is a patch against 2.6.22-rc3 that adds support for both the PATA
and SATA portions of the Marvell AHCI-like chip.
The architecture for PATA is quite nice, mimicing AHCI very closely.
Basic port scanning, interrupt handling, freezing and thawing is the
same, and uses the same register
Here is a patch against 2.6.22-rc3 that adds support for both the PATA
and SATA portions of the Marvell AHCI-like chip.
The architecture for PATA is quite nice, mimicing AHCI very closely.
Basic port scanning, interrupt handling, freezing and thawing is the
same, and uses the same register
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