Re: [PATCH] Add an option for the VIA C7 which sets appropriate L1 cache

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has a cache line length of 64 according to http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets gcc to -march=686 and selects the correct cache shift. This version adds it to include/asm-i386/module.h

[PATCH] Add an option for the VIA C7 which sets appropriate L1 cache

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has a cache line length of 64 according to http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets gcc to -march=686 and selects the correct cache shift. Signed-off-by: Simon Arlott <[EMAIL PROTECTED]>

[PATCH] Add an option for the VIA C7 which sets appropriate L1 cache

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has a cache line length of 64 according to http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets gcc to -march=686 and selects the correct cache shift. Signed-off-by: Simon Arlott [EMAIL PROTECTED] ---

Re: [PATCH] Add an option for the VIA C7 which sets appropriate L1 cache

The VIA C7 is a 686 (with TSC) that supports MMX, SSE and SSE2, it also has a cache line length of 64 according to http://www.digit-life.com/articles2/cpu/rmma-via-c7.html. This patch sets gcc to -march=686 and selects the correct cache shift. This version adds it to include/asm-i386/module.h