Re: 答复: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-29 Thread Rafael J. Wysocki
om; pa...@ucw.cz; t...@linutronix.de; > mi...@redhat.com; h...@zytor.com; x...@kernel.org; linux...@kernel.org; > linux-kernel@vger.kernel.org; Bruce Chang (VAS); Cooper Yan(BJ-RD); Qiyuan > Wang(BJ-RD); Benjamin Pan; Luke Lin; Tim Guo(BJ-RD); Cobe Chen(BJ-RD); > Jiangbo Wang(BJ-RD) >

Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-12 Thread Ingo Molnar
* Rafael J. Wysocki wrote: > On Monday, March 12, 2018 9:40:33 AM CET Ingo Molnar wrote: > > > > * David Wang wrote: > > > > > [David] pr->flags.has_cst means BIOS define valid C state table. And at > > > lease > > > define 2 entries. On all centaur platform which support C3, this > > > c

Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-12 Thread Rafael J. Wysocki
On Monday, March 12, 2018 9:40:33 AM CET Ingo Molnar wrote: > > * David Wang wrote: > > > [David] pr->flags.has_cst means BIOS define valid C state table. And at > > lease > > define 2 entries. On all centaur platform which support C3, this condition > > is > > always true. > > > [David] J

Re: 答复: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-12 Thread Ingo Molnar
* David Wang wrote: > [David] pr->flags.has_cst means BIOS define valid C state table. And at > lease > define 2 entries. On all centaur platform which support C3, this condition is > always true. > [David] Just as the following comment said, we need not execute WBINVD and > ARB_DISABLE/AR

Re: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-04 Thread Ingo Molnar
* David Wang wrote: > For Centaur CPU, the ucode will make sure that each CPU core can keep cache > coherency with each other when the CPU core entering to any C state. So the > cache flush operations when enter C3 is not necessary and will cause large > C3 enter/exit latency. > And the bus maste

Re: [PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-02 Thread Rafael J. Wysocki
On Friday, March 2, 2018 5:11:48 AM CET David Wang wrote: > For Centaur CPU, the ucode will make sure that each CPU core can keep cache > coherency with each other when the CPU core entering to any C state. So the > cache flush operations when enter C3 is not necessary and will cause large > C3 ent

[PATCH] Delete some unusefull operations for centaur CPU/platform

2018-03-01 Thread David Wang
For Centaur CPU, the ucode will make sure that each CPU core can keep cache coherency with each other when the CPU core entering to any C state. So the cache flush operations when enter C3 is not necessary and will cause large C3 enter/exit latency. And the bus master disable operation when CPU cor