On 02/03/21 01:59, Sean Christopherson wrote:
+ svm->vmcb->save.cr2 = svm->vcpu.arch.cr2 = vmcb12->save.cr2;
Same question for VMCB_CR2.
Besides the question of how much AMD processors actually use the clean
bits (a quick test suggests "not much"), in this specific case I suspect
that
On 02/03/21 13:56, Cathy Avery wrote:
On 3/1/21 7:59 PM, Sean Christopherson wrote:
On Mon, Mar 01, 2021, Cathy Avery wrote:
svm->nested.vmcb12_gpa = 0;
+ svm->nested.last_vmcb12_gpa = 0;
This should not be 0 to avoid a false match. "-1" should be okay.
kvm_set_rflags(&
On 3/1/21 7:59 PM, Sean Christopherson wrote:
On Mon, Mar 01, 2021, Cathy Avery wrote:
kvm_set_rflags(&svm->vcpu, vmcb12->save.rflags | X86_EFLAGS_FIXED);
svm_set_efer(&svm->vcpu, vmcb12->save.efer);
svm_set_cr0(&svm->vcpu, vmcb12->save.cr0);
svm_set_cr4(&svm->vcp
On Mon, Mar 01, 2021, Cathy Avery wrote:
> kvm_set_rflags(&svm->vcpu, vmcb12->save.rflags | X86_EFLAGS_FIXED);
> svm_set_efer(&svm->vcpu, vmcb12->save.efer);
> svm_set_cr0(&svm->vcpu, vmcb12->save.cr0);
> svm_set_cr4(&svm->vcpu, vmcb12->save.cr4);
Why not utilize VMCB_CR?
Use the vmcb12 control clean field to determine which vmcb12.save
registers were marked dirty in order to minimize register copies
when switching from L1 to L2. Those L12 registers marked as dirty need
to be copied to L2's vmcb as they will be used to update the vmcb
state cache for the L2 VMRUN.
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