On 13/05/15 19:49, Kevin Cernekee wrote:
> On Wed, May 13, 2015 at 6:49 PM, Leonid Yegoshin
> wrote:
>> Some MIPS CPUs have an aggressive speculative load and may erroneuosly load
>> some cache line in the middle of DMA transaction. CPU discards result but
>> cache
>> doesn't. If DMA happens from
On Wed, May 13, 2015 at 6:49 PM, Leonid Yegoshin
wrote:
> Some MIPS CPUs have an aggressive speculative load and may erroneuosly load
> some cache line in the middle of DMA transaction. CPU discards result but
> cache
> doesn't. If DMA happens from device then additional cache invalidation is
>
Some MIPS CPUs have an aggressive speculative load and may erroneuosly load
some cache line in the middle of DMA transaction. CPU discards result but cache
doesn't. If DMA happens from device then additional cache invalidation is needed
on that CPU's after DMA.
Found in test.
Signed-off-by: Leoni
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