Hi Bjorn,
On 02/22/2018 08:39 PM, Bjorn Helgaas wrote:
On Thu, Feb 22, 2018 at 06:43:34PM +0530, George Cherian wrote:
On 02/22/2018 04:50 AM, Bjorn Helgaas wrote:
On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
On 02/21/2018 03:24 PM, Lukas Wunner wrote:
On Wed, Feb 21, 201
On Thu, Feb 22, 2018 at 06:43:34PM +0530, George Cherian wrote:
> On 02/22/2018 04:50 AM, Bjorn Helgaas wrote:
> > On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
> > > On 02/21/2018 03:24 PM, Lukas Wunner wrote:
> > > > On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote
Hi Bjorn,
On 02/22/2018 04:50 AM, Bjorn Helgaas wrote:
On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
On 02/21/2018 03:24 PM, Lukas Wunner wrote:
On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote:
I will explain the setup used
To the Cavium ThunderX RC the follow
On Thursday, February 22, 2018 9:35:43 AM CET Lukas Wunner wrote:
> On Wed, Feb 21, 2018 at 05:20:40PM -0600, Bjorn Helgaas wrote:
> > On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
> > > I have found another configuration where this fails.
> > > Following is the configuration
> >
On Wed, Feb 21, 2018 at 05:20:40PM -0600, Bjorn Helgaas wrote:
> On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
> > I have found another configuration where this fails.
> > Following is the configuration
> > 1) Connected a PCIe Intel i40 card under the root port.
> > 2) unbind the
On Wed, Feb 21, 2018 at 04:25:08PM +0530, George Cherian wrote:
> On 02/21/2018 03:24 PM, Lukas Wunner wrote:
> > On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote:
> > > I will explain the setup used
> > > To the Cavium ThunderX RC the following PLX device is connected.
> > > PLX Tech
Hi Lukas,
On 02/21/2018 03:24 PM, Lukas Wunner wrote:
On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote:
I will explain the setup used
To the Cavium ThunderX RC the following PLX device is connected.
PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI Express Gen 3 (8.0 GT/s)
Switch
On Wed, Feb 21, 2018 at 02:58:13PM +0530, George Cherian wrote:
> I will explain the setup used
> To the Cavium ThunderX RC the following PLX device is connected.
> PLX Technology, Inc. PEX 8747 48-Lane, 5-Port PCI Express Gen 3 (8.0 GT/s)
> Switch
> There is no device connected downstream to the P
Hi Bjorn,
On 02/21/2018 12:30 AM, Bjorn Helgaas wrote:
[+cc Huang]
On Tue, Feb 20, 2018 at 02:54:33AM +0100, Lukas Wunner wrote:
On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote:
On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
On Fri, Feb 16, 2018 at 01:40:
[+cc Huang]
On Tue, Feb 20, 2018 at 02:54:33AM +0100, Lukas Wunner wrote:
> On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote:
> > On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
> > > On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> > > > On Fr
On Tuesday, February 20, 2018 2:54:33 AM CET Lukas Wunner wrote:
> On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote:
> > On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
> > > On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> > > > On Friday, Febr
On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote:
> On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
> > On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> > > On Friday, February 16, 2018 12:39:00 AM CET Bjorn Helgaas wrote:
> > > > On Thu, Feb 15
On Mon, Feb 19, 2018 at 12:21:56PM +0100, Rafael J. Wysocki wrote:
> On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
> > On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> > > On Friday, February 16, 2018 12:39:00 AM CET Bjorn Helgaas wrote:
> > > > My questions
Hi Bjorn, Rafael, others,
On 02/15/2018 06:39 PM, Bjorn Helgaas wrote:
> On Thu, Feb 15, 2018 at 10:57:25PM +0100, Rafael J. Wysocki wrote:
>> On Wednesday, February 14, 2018 9:16:53 PM CET Bjorn Helgaas wrote:
>>> On Wed, Feb 14, 2018 at 04:58:08PM +0530, George Cherian wrote:
On 02/13/2018
On Friday, February 16, 2018 9:34:34 PM CET Bjorn Helgaas wrote:
> On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> > On Friday, February 16, 2018 12:39:00 AM CET Bjorn Helgaas wrote:
> > > On Thu, Feb 15, 2018 at 10:57:25PM +0100, Rafael J. Wysocki wrote:
> > > > On Wednesday,
On Fri, Feb 16, 2018 at 01:40:37PM +0100, Rafael J. Wysocki wrote:
> On Friday, February 16, 2018 12:39:00 AM CET Bjorn Helgaas wrote:
> > On Thu, Feb 15, 2018 at 10:57:25PM +0100, Rafael J. Wysocki wrote:
> > > On Wednesday, February 14, 2018 9:16:53 PM CET Bjorn Helgaas wrote:
> > > > On Wed, Feb
On Friday, February 16, 2018 12:39:00 AM CET Bjorn Helgaas wrote:
> On Thu, Feb 15, 2018 at 10:57:25PM +0100, Rafael J. Wysocki wrote:
> > On Wednesday, February 14, 2018 9:16:53 PM CET Bjorn Helgaas wrote:
> > > On Wed, Feb 14, 2018 at 04:58:08PM +0530, George Cherian wrote:
> > > > On 02/13/2018
On Thu, Feb 15, 2018 at 10:57:25PM +0100, Rafael J. Wysocki wrote:
> On Wednesday, February 14, 2018 9:16:53 PM CET Bjorn Helgaas wrote:
> > On Wed, Feb 14, 2018 at 04:58:08PM +0530, George Cherian wrote:
> > > On 02/13/2018 08:39 PM, Bjorn Helgaas wrote:
> > > >On Fri, Feb 02, 2018 at 07:00:46AM +
On Wednesday, February 14, 2018 9:16:53 PM CET Bjorn Helgaas wrote:
> [+cc Rafael, PM question below]
+Mika
> On Wed, Feb 14, 2018 at 04:58:08PM +0530, George Cherian wrote:
> > On 02/13/2018 08:39 PM, Bjorn Helgaas wrote:
> > >On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote:
> > >
[+cc Rafael, PM question below]
On Wed, Feb 14, 2018 at 04:58:08PM +0530, George Cherian wrote:
> On 02/13/2018 08:39 PM, Bjorn Helgaas wrote:
> >On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote:
> >>The PCIe Controller on Cavium ThunderX2 processors does not
> >>respond to downstrea
Hi Bjorn,
Thanks for the review.
On 02/13/2018 08:39 PM, Bjorn Helgaas wrote:
[+cc Lorenzo]
On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote:
The PCIe Controller on Cavium ThunderX2 processors does not
respond to downstream CFG/ECFG cycles when root port is
in power management D
[+cc Lorenzo]
On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote:
> The PCIe Controller on Cavium ThunderX2 processors does not
> respond to downstream CFG/ECFG cycles when root port is
> in power management D3-hot state.
I think you're talking about the CPU initiating a config cycle
On Fri, Feb 02, 2018 at 07:00:46AM +, George Cherian wrote:
> The PCIe Controller on Cavium ThunderX2 processors does not
> respond to downstream CFG/ECFG cycles when root port is
> in power management D3-hot state.
>
> In our tests the above mentioned errata causes the following crash when
>
The PCIe Controller on Cavium ThunderX2 processors does not
respond to downstream CFG/ECFG cycles when root port is
in power management D3-hot state.
In our tests the above mentioned errata causes the following crash when
the downstream endpoint config space is accessed, while root port is in
D3 s
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