On Mon, Oct 05, 2020 at 05:43:51PM +0530, Vidya Sagar wrote:
> Use ATU region-3 and region-0 to setup mapping for prefetchable and
> non-prefetchable memory regions respectively only if their respective CPU
> and bus addresses are different.
>
The commit subject and log must be rewritten. You sho
On Tue, Oct 20, 2020 at 07:03:59PM +0530, Vidya Sagar wrote:
>
>
> On 10/20/2020 6:50 PM, Lorenzo Pieralisi wrote:
> > External email: Use caution opening links or attachments
> >
> >
> > On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
> > > Hi Lorenzo, Rob, Gustavo,
> > > Could yo
On 10/20/2020 6:50 PM, Lorenzo Pieralisi wrote:
External email: Use caution opening links or attachments
On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
Hi Lorenzo, Rob, Gustavo,
Could you please review this change?
Next cycle - we are in the middle of the merge window and I
On Mon, Oct 19, 2020 at 11:21:54AM +0530, Vidya Sagar wrote:
> Hi Lorenzo, Rob, Gustavo,
> Could you please review this change?
Next cycle - we are in the middle of the merge window and I am not
queueing any more patches.
Thanks,
Lorenzo
> Thanks,
> Vidya Sagar
>
> On 10/5/2020 5:43 PM, Vidya S
Hi Lorenzo, Rob, Gustavo,
Could you please review this change?
Thanks,
Vidya Sagar
On 10/5/2020 5:43 PM, Vidya Sagar wrote:
Use ATU region-3 and region-0 to setup mapping for prefetchable and
non-prefetchable memory regions respectively only if their respective CPU
and bus addresses are differe
Use ATU region-3 and region-0 to setup mapping for prefetchable and
non-prefetchable memory regions respectively only if their respective CPU
and bus addresses are different.
Signed-off-by: Vidya Sagar
---
.../pci/controller/dwc/pcie-designware-host.c | 44 ---
drivers/pci/contro
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