> * a value of 1 for all rates below 2400 (On 8250, fifo is set to 1
> for such rates)
> * a value of 2 for 2400 and 4800
> * a value of 4 for 9600 (which is the default on the 8250 for all
> rates above 2400)
> * a value of 8 for 19200
> * a value of 16 for 38400 and above (on UCC_UART, maxidl is
Le 16/08/2012 17:21, Alan Cox a écrit :
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable
Le 16/08/2012 17:21, Alan Cox a écrit :
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable
* a value of 1 for all rates below 2400 (On 8250, fifo is set to 1
for such rates)
* a value of 2 for 2400 and 4800
* a value of 4 for 9600 (which is the default on the 8250 for all
rates above 2400)
* a value of 8 for 19200
* a value of 16 for 38400 and above (on UCC_UART, maxidl is set to
> MAX_IDL: Maximum idle characters. When a character is received, the
> receiver begins counting idle characters. If MAX_IDL idle characters
> are received before the next data character, an idle timeout occurs
> and the buffer is closed,
> generating a maskable interrupt request to the core to
Le 16/08/2012 16:29, Alan Cox a écrit :
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the
> The PowerPC CPM is working differently. It doesn't use a fifo but
> buffers. Buffers are handed to the microprocessor only when they are
> full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the FIFO on an IRQ
> buffers are
Le 14/08/2012 16:52, Alan Cox a écrit :
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy wrote:
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE
Le 14/08/2012 16:52, Alan Cox a écrit :
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy christophe.le...@c-s.fr wrote:
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the FIFO on an IRQ
buffers are
Le 16/08/2012 16:29, Alan Cox a écrit :
The PowerPC CPM is working differently. It doesn't use a fifo but
buffers. Buffers are handed to the microprocessor only when they are
full or after a timeout period which is adjustable. In the driver, the
Which is different how - remembering we empty the
MAX_IDL: Maximum idle characters. When a character is received, the
receiver begins counting idle characters. If MAX_IDL idle characters
are received before the next data character, an idle timeout occurs
and the buffer is closed,
generating a maskable interrupt request to the core to
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy wrote:
> Hello,
>
> I'm not sure who to address this Patch to either
>
> It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
> The problem is that with the actual code, the driver waits 32 IDLE patterns
> before returning the
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns
before returning the received data to the upper level. It means for instance
about 1 second at 300
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns
before returning the received data to the upper level. It means for instance
about 1 second at 300
On Tue, 14 Aug 2012 16:26:28 +0200
Christophe Leroy christophe.le...@c-s.fr wrote:
Hello,
I'm not sure who to address this Patch to either
It fixes a delay issue with CPM UART driver on Powerpc MPC8xx.
The problem is that with the actual code, the driver waits 32 IDLE patterns
before
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