Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Anup Patel
On Wed, Mar 27, 2019 at 7:39 PM Gary Guo wrote: > > I think my code already get all the caveats cases covered. The only > thing my code is missing is handling the case when ASID is not > supported. Maybe it is better to work based on that instead? Well, I have also spend enough time hardening thi

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Anup Patel
On Wed, Mar 27, 2019 at 7:08 PM Gary Guo wrote: > > On 27/03/2019 11:42, Anup Patel wrote: > > On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote: > >> > >> Hi Anup, > >> > >> This won't work in an actual hardware with ASID support. There're more > > > > Can you elaborate why > > > > > This implement

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Gary Guo
I think my code already get all the caveats cases covered. The only thing my code is missing is handling the case when ASID is not supported. Maybe it is better to work based on that instead? On 27/03/2019 14:02, Anup Patel wrote: > On Wed, Mar 27, 2019 at 7:12 PM Gary Guo wrote: >> >> I would

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Anup Patel
On Wed, Mar 27, 2019 at 7:12 PM Gary Guo wrote: > > I would also like to mention that your code assumes 64-bit atomics > support which we don't have on 32-bit systems. Using 32-bit to track > ASID generations isn't sufficient and will cause overflows. That's why I > have asid_generation_overflow t

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Gary Guo
I would also like to mention that your code assumes 64-bit atomics support which we don't have on 32-bit systems. Using 32-bit to track ASID generations isn't sufficient and will cause overflows. That's why I have asid_generation_overflow to handle the case (this is super error-prone as well).

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Gary Guo
On 27/03/2019 11:42, Anup Patel wrote: > On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote: >> >> Hi Anup, >> >> This won't work in an actual hardware with ASID support. There're more > > Can you elaborate why > > > This implementation is based on Linux ARM64 ASID allocator which is > tested for la

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Anup Patel
On Wed, Mar 27, 2019 at 4:57 PM Gary Guo wrote: > > Hi Anup, > > This won't work in an actual hardware with ASID support. There're more Can you elaborate why? This implementation is based on Linux ARM64 ASID allocator which is tested for large number of CPUs on real HW. > interactions with TLB

Re: [PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Gary Guo
Hi Anup, This won't work in an actual hardware with ASID support. There're more interactions with TLB flushes that need to be considered. You won't see this on both QEMU and SiFive board, as QEMU does not have ASID, so it pretends that ASID is supported by just flushing its TLB everytime you c

[PATCH] RISC-V: Implement ASID allocator

2019-03-27 Thread Anup Patel
Currently, we do local TLB flush on every MM switch. This is very harsh on performance because we are forcing page table walks after every MM switch. This patch implements ASID allocator for assigning an ASID to every MM context. The number of ASIDs are limited in HW so we create a logical entity