Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

Hi David, Thanks for the reply. On Wed, Feb 10, 2016 at 10:42:18AM -0800, David Daney wrote: > On 02/10/2016 10:15 AM, Will Deacon wrote: > >On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: > >>On 02/10/2016 01:28 AM, Will Deacon wrote: > >>>On Tue, Feb 09, 2016 at 11:29:16AM -0800,

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

Hi David, Thanks for the reply. On Wed, Feb 10, 2016 at 10:42:18AM -0800, David Daney wrote: > On 02/10/2016 10:15 AM, Will Deacon wrote: > >On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: > >>On 02/10/2016 01:28 AM, Will Deacon wrote: > >>>On Tue, Feb 09, 2016 at 11:29:16AM -0800,

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/10/2016 10:15 AM, Will Deacon wrote: On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: On 02/10/2016 01:28 AM, Will Deacon wrote: On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: > On 02/10/2016 01:28 AM, Will Deacon wrote: > >On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: > >>From: Andrew Pinski > >> > >>On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > >>instructions may cause the

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/10/2016 01:28 AM, Will Deacon wrote: On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This patch

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: > From: Andrew Pinski > > On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > instructions may cause the icache to become invalid if it contains > data for a non-current ASID. > > This patch implements the workaround (which

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/10/2016 01:28 AM, Will Deacon wrote: On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: > On 02/10/2016 01:28 AM, Will Deacon wrote: > >On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: > >>From: Andrew Pinski > >> > >>On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI >

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/10/2016 10:15 AM, Will Deacon wrote: On Wed, Feb 10, 2016 at 10:08:17AM -0800, David Daney wrote: On 02/10/2016 01:28 AM, Will Deacon wrote: On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts,

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, Feb 09, 2016 at 11:29:16AM -0800, David Daney wrote: > From: Andrew Pinski > > On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > instructions may cause the icache to become invalid if it contains > data for a non-current ASID. > > This patch implements the

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, 9 Feb 2016 11:59:10 -0800 David Daney wrote: > On 02/09/2016 11:52 AM, Marc Zyngier wrote: > > On Tue, 9 Feb 2016 11:29:16 -0800 > > David Daney wrote: > > > > Hi David, > > > >> From: Andrew Pinski > >> > >> On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > >> instructions

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/09/2016 11:52 AM, Marc Zyngier wrote: On Tue, 9 Feb 2016 11:29:16 -0800 David Daney wrote: Hi David, From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, 9 Feb 2016 11:29:16 -0800 David Daney wrote: Hi David, > From: Andrew Pinski > > On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > instructions may cause the icache to become invalid if it contains > data for a non-current ASID. > > This patch implements the workaround

[PATCH] arm64: Add workaround for Cavium erratum 27456

From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This patch implements the workaround (which flushes the local icache when switching the mm) by using code patching.

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On 02/09/2016 11:52 AM, Marc Zyngier wrote: On Tue, 9 Feb 2016 11:29:16 -0800 David Daney wrote: Hi David, From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, 9 Feb 2016 11:59:10 -0800 David Daney wrote: > On 02/09/2016 11:52 AM, Marc Zyngier wrote: > > On Tue, 9 Feb 2016 11:29:16 -0800 > > David Daney wrote: > > > > Hi David, > > > >> From: Andrew Pinski > >> > >> On

Re: [PATCH] arm64: Add workaround for Cavium erratum 27456

On Tue, 9 Feb 2016 11:29:16 -0800 David Daney wrote: Hi David, > From: Andrew Pinski > > On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI > instructions may cause the icache to become invalid if it contains > data for a non-current ASID. >

[PATCH] arm64: Add workaround for Cavium erratum 27456

From: Andrew Pinski On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI instructions may cause the icache to become invalid if it contains data for a non-current ASID. This patch implements the workaround (which flushes the local icache when switching the mm) by using