Il 13/01/21 05:37, Danny Lin ha scritto:
On Tue, Jan 12, 2021 at 8:04 pm, AngeloGioacchino Del Regno
wrote:
Il 12/01/21 15:59, Alexey Minnekhanov ha scritto:
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
one
On Tue, Jan 12, 2021 at 8:04 pm, AngeloGioacchino Del Regno
wrote:
Il 12/01/21 15:59, Alexey Minnekhanov ha scritto:
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
ones?
But downstream sdm660.dtsi has a prope
Il 12/01/21 15:59, Alexey Minnekhanov ha scritto:
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
ones?
But downstream sdm660.dtsi has a property "efficiency" [1] with values
which are larger for cores 100-103 than
Hi!
I always had a feeling something is not right in those cpu
definitions, so cpus with reg 100-103 are little cores, and 0-3 big
ones?
But downstream sdm660.dtsi has a property "efficiency" [1] with values
which are larger for cores 100-103 than for 0-3 cores (1638 > 1024),
I'm confused...
Prope
sdm660 has a big.LITTLE 4+4 CPU setup with CPUs 0-3 being little cores
and CPUs 4-7 being big cores. The big cores have higher IPC, so they
should have the higher capacity-dmips-mhz, not the other way around as
the device tree currently describes it. Fix the incorrect CPU map to
improve EAS schedul
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