Re: [PATCH] arm64: invalidate TLB before turning MMU on

2018-12-13 Thread Qian Cai
On Thu, 2018-12-13 at 10:44 +, James Morse wrote: > The kernel should already handle this, as we don't trust the bootloader to > clean > up either. > > In arch/arm64/mm/proc.S::__cpu_setup() > > /* > > * __cpu_setup > > * > > * Initialise the processor for turning the MMU on.  Return in

Re: [PATCH] arm64: invalidate TLB before turning MMU on

2018-12-13 Thread Qian Cai
On Thu, 2018-12-13 at 11:10 +0530, Bhupesh Sharma wrote: > Hi Qian Cai, > > On Thu, Dec 13, 2018 at 10:53 AM Qian Cai wrote: > > > > On this HPE Apollo 70 arm64 server with 256 CPUs, triggering a crash > > dump just hung. It has 4 threads on each core. Each 2-core share a same > > L1 and L2

Re: [PATCH] arm64: invalidate TLB before turning MMU on

2018-12-13 Thread James Morse
Hi Qian, On 13/12/2018 05:22, Qian Cai wrote: > On this HPE Apollo 70 arm64 server with 256 CPUs, triggering a crash > dump just hung. It has 4 threads on each core. Each 2-core share a same > L1 and L2 caches, so that is 8 CPUs shares those. All CPUs share a same > L3 cache. > > It turned out

Re: [PATCH] arm64: invalidate TLB before turning MMU on

2018-12-12 Thread Bhupesh Sharma
Hi Qian Cai, On Thu, Dec 13, 2018 at 10:53 AM Qian Cai wrote: > > On this HPE Apollo 70 arm64 server with 256 CPUs, triggering a crash > dump just hung. It has 4 threads on each core. Each 2-core share a same > L1 and L2 caches, so that is 8 CPUs shares those. All CPUs share a same > L3 cache. >

[PATCH] arm64: invalidate TLB before turning MMU on

2018-12-12 Thread Qian Cai
On this HPE Apollo 70 arm64 server with 256 CPUs, triggering a crash dump just hung. It has 4 threads on each core. Each 2-core share a same L1 and L2 caches, so that is 8 CPUs shares those. All CPUs share a same L3 cache. It turned out that this was due to the TLB contained stale entries (or