On 2019/3/30 上午6:18, Stephen Boyd wrote:
> Quoting qiaozhou (2019-03-23 07:08:35)
>> From: Qiao Zhou
>>
>> add clock driver support for ASR AquilaC SoC.
>>
>> We add clk-gate, clk-mix, and clk-pll drivers:
>> 1. clk-gate driver is for regisers which have different enable/disable bits
>> to
Quoting qiaozhou (2019-03-23 07:08:35)
> From: Qiao Zhou
>
> add clock driver support for ASR AquilaC SoC.
>
> We add clk-gate, clk-mix, and clk-pll drivers:
> 1. clk-gate driver is for regisers which have different enable/disable bits
> to control gating.
> 2. clk-mix driver is for registers
On 2019/3/26 下午7:54, Dan Carpenter wrote:
> On Sat, Mar 23, 2019 at 10:08:35PM +0800, qiaozhou wrote:
>> From: Qiao Zhou
>>
>> add clock driver support for ASR AquilaC SoC.
>>
>> We add clk-gate, clk-mix, and clk-pll drivers:
>> 1. clk-gate driver is for regisers which have different
On Sat, Mar 23, 2019 at 10:08:35PM +0800, qiaozhou wrote:
> From: Qiao Zhou
>
> add clock driver support for ASR AquilaC SoC.
>
> We add clk-gate, clk-mix, and clk-pll drivers:
> 1. clk-gate driver is for regisers which have different enable/disable bits
> to control gating.
> 2. clk-mix driver
From: Qiao Zhou
add clock driver support for ASR AquilaC SoC.
We add clk-gate, clk-mix, and clk-pll drivers:
1. clk-gate driver is for regisers which have different enable/disable bits
to control gating.
2. clk-mix driver is for registers which request to set div and mux
bits at the same time.
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