Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Quoting Paul Cercueil (2019-04-29 13:53:11) > Hi Stephen, > > Le jeu. 18 avril 2019 à 23:58, Stephen Boyd a > écrit : > > Quoting Paul Cercueil (2019-04-17 04:24:20) > >> The pixel clock is directly connected to the output of the PLL, and > >> not > >> to the /2 divider. > >> > >> Cc: sta..

Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Hi Stephen, Le jeu. 18 avril 2019 à 23:58, Stephen Boyd a écrit : Quoting Paul Cercueil (2019-04-17 04:24:20) The pixel clock is directly connected to the output of the PLL, and not to the /2 divider. Cc: sta...@vger.kernel.org Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")

Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Quoting Paul Cercueil (2019-04-17 04:24:20) > The pixel clock is directly connected to the output of the PLL, and not > to the /2 divider. > > Cc: sta...@vger.kernel.org > Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver") > Signed-off-by: Paul Cercueil > --- Applied to clk-next

Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Quoting Paul Cercueil (2019-04-17 16:53:53) > Hi Stephen, > > Le jeu. 18 avril 2019 à 1:48, Stephen Boyd a écrit > : > > Quoting Paul Cercueil (2019-04-17 04:24:20) > >> The pixel clock is directly connected to the output of the PLL, and > >> not > >> to the /2 divider. > >> > >> Cc: sta...

Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Hi Stephen, Le jeu. 18 avril 2019 à 1:48, Stephen Boyd a écrit : Quoting Paul Cercueil (2019-04-17 04:24:20) The pixel clock is directly connected to the output of the PLL, and not to the /2 divider. Cc: sta...@vger.kernel.org Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver")

Re: [PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

Quoting Paul Cercueil (2019-04-17 04:24:20) > The pixel clock is directly connected to the output of the PLL, and not > to the /2 divider. > > Cc: sta...@vger.kernel.org > Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver") > Signed-off-by: Paul Cercueil > --- Is this breaking something

[PATCH] clk: ingenic/jz4725b: Fix parent of pixel clock

The pixel clock is directly connected to the output of the PLL, and not to the /2 divider. Cc: sta...@vger.kernel.org Fixes: 226dfa4726eb ("clk: Add Ingenic jz4725b CGU driver") Signed-off-by: Paul Cercueil --- drivers/clk/ingenic/jz4725b-cgu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(