Am Dienstag, 7. Juli 2015, 17:48:45 schrieb James Liao:
> Hi Heiko,
>
> On Tue, 2015-07-07 at 11:34 +0200, Heiko Stübner wrote:
> > > > > @@ -135,16 +138,26 @@ static void mtk_pll_calc_values(struct
> > > > > mtk_clk_pll
> > > > > *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin)
> > > > >
> > >
Hi Heiko,
On Tue, 2015-07-07 at 11:34 +0200, Heiko Stübner wrote:
> > > > @@ -135,16 +138,26 @@ static void mtk_pll_calc_values(struct mtk_clk_pll
> > > > *pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin)
> > > >
> > > > {
> > > >
> > > > unsigned long fmin = 1000 * MHZ;
> > > >
> > >
Hi James,
Am Dienstag, 7. Juli 2015, 17:28:38 schrieb James Liao:
> On Tue, 2015-07-07 at 10:58 +0200, Heiko Stübner wrote:
> > > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,
> > > \
> > > + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
> > > +
Hi Heiko,
On Tue, 2015-07-07 at 10:58 +0200, Heiko Stübner wrote:
> > +#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,
> > \
> > + _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
> > + _pcw_shift)
Hi James,
Am Dienstag, 2. Juni 2015, 13:26:00 schrieb James Liao:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173 MMPLL frequency setting, includes:
>
> 1. Add div-rate
Hi,
Does anyone have comments for this patch?
Best regards,
James
On Tue, 2015-06-02 at 13:26 +0800, James Liao wrote:
> MT8173 MMPLL frequency settings are different from common PLLs.
> It needs different post divider settings for some ranges of frequency.
> This patch add support for MT8173
Hi,
Does anyone have comments for this patch?
Best regards,
James
On Tue, 2015-06-02 at 13:26 +0800, James Liao wrote:
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173
Hi James,
Am Dienstag, 2. Juni 2015, 13:26:00 schrieb James Liao:
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:
1. Add div-rate table
Am Dienstag, 7. Juli 2015, 17:48:45 schrieb James Liao:
Hi Heiko,
On Tue, 2015-07-07 at 11:34 +0200, Heiko Stübner wrote:
@@ -135,16 +138,26 @@ static void mtk_pll_calc_values(struct
mtk_clk_pll
*pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin)
{
Hi Heiko,
On Tue, 2015-07-07 at 10:58 +0200, Heiko Stübner wrote:
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,
\
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+ _pcw_shift) \
+
Hi Heiko,
On Tue, 2015-07-07 at 11:34 +0200, Heiko Stübner wrote:
@@ -135,16 +138,26 @@ static void mtk_pll_calc_values(struct mtk_clk_pll
*pll, u32 *pcw, u32 *postdiv, u32 freq, u32 fin)
{
unsigned long fmin = 1000 * MHZ;
+ const unsigned long
Hi James,
Am Dienstag, 7. Juli 2015, 17:28:38 schrieb James Liao:
On Tue, 2015-07-07 at 10:58 +0200, Heiko Stübner wrote:
+#define PLL(_id, _name, _reg, _pwr_reg, _en_mask, _flags, _pcwbits,
\
+ _pd_reg, _pd_shift, _tuner_reg, _pcw_reg, \
+
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:
1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4
MT8173 MMPLL frequency settings are different from common PLLs.
It needs different post divider settings for some ranges of frequency.
This patch add support for MT8173 MMPLL frequency setting, includes:
1. Add div-rate table for PLLs.
2. Increase the max ost divider setting from 3 (/8) to 4
14 matches
Mail list logo
