Am Mittwoch, 24. September 2014, 13:21:57 schrieb Doug Anderson:
> Hi,
>
> On Thu, Aug 7, 2014 at 5:57 AM, Heiko Stübner wrote:
> > PLLs on Rockchip platforms report their locking state in an external
> > register situated in the "General Register Files" which is provided
> > through a syscon
Hi,
On Thu, Aug 7, 2014 at 5:57 AM, Heiko Stübner wrote:
> PLLs on Rockchip platforms report their locking state in an external
> register situated in the "General Register Files" which is provided
> through a syscon device.
>
> When the initial clk init runs, this syscon is of course not yet
>
Hi,
On Thu, Aug 7, 2014 at 5:57 AM, Heiko Stübner he...@sntech.de wrote:
PLLs on Rockchip platforms report their locking state in an external
register situated in the General Register Files which is provided
through a syscon device.
When the initial clk init runs, this syscon is of course
Am Mittwoch, 24. September 2014, 13:21:57 schrieb Doug Anderson:
Hi,
On Thu, Aug 7, 2014 at 5:57 AM, Heiko Stübner he...@sntech.de wrote:
PLLs on Rockchip platforms report their locking state in an external
register situated in the General Register Files which is provided
through a
Heiko,
On 08/07/2014 08:57 PM, Heiko Stübner wrote:
PLLs on Rockchip platforms report their locking state in an external
register situated in the "General Register Files" which is provided
through a syscon device.
When the initial clk init runs, this syscon is of course not yet
available,
Heiko,
On 08/07/2014 08:57 PM, Heiko Stübner wrote:
PLLs on Rockchip platforms report their locking state in an external
register situated in the General Register Files which is provided
through a syscon device.
When the initial clk init runs, this syscon is of course not yet
available, making
PLLs on Rockchip platforms report their locking state in an external
register situated in the "General Register Files" which is provided
through a syscon device.
When the initial clk init runs, this syscon is of course not yet
available, making it impossible to set PLLs to other frequencies
PLLs on Rockchip platforms report their locking state in an external
register situated in the General Register Files which is provided
through a syscon device.
When the initial clk init runs, this syscon is of course not yet
available, making it impossible to set PLLs to other frequencies
through
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