Re: [PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-12 Thread Heiko Stübner
Am Freitag, 12. April 2019, 20:02:55 CEST schrieb Matthias Kaehlcke: > On Fri, Apr 12, 2019 at 11:30:37AM +0200, Heiko Stübner wrote: > > Am Freitag, 12. April 2019, 02:16:57 CEST schrieb Matthias Kaehlcke: > > > Hi Heiko, > > > > > > On Thu, Apr 11, 2019 at 09:03:07PM +0200, Heiko Stübner wrote:

Re: [PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-12 Thread Matthias Kaehlcke
On Fri, Apr 12, 2019 at 11:30:37AM +0200, Heiko Stübner wrote: > Am Freitag, 12. April 2019, 02:16:57 CEST schrieb Matthias Kaehlcke: > > Hi Heiko, > > > > On Thu, Apr 11, 2019 at 09:03:07PM +0200, Heiko Stübner wrote: > > > Hi Matthias, > > > > > > Am Donnerstag, 11. April 2019, 19:59:17 CEST

Re: [PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-12 Thread Heiko Stübner
Am Freitag, 12. April 2019, 02:16:57 CEST schrieb Matthias Kaehlcke: > Hi Heiko, > > On Thu, Apr 11, 2019 at 09:03:07PM +0200, Heiko Stübner wrote: > > Hi Matthias, > > > > Am Donnerstag, 11. April 2019, 19:59:17 CEST schrieb Matthias Kaehlcke: > > > The USB PHY clock can be configured as

Re: [PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-11 Thread Matthias Kaehlcke
Hi Heiko, On Thu, Apr 11, 2019 at 09:03:07PM +0200, Heiko Stübner wrote: > Hi Matthias, > > Am Donnerstag, 11. April 2019, 19:59:17 CEST schrieb Matthias Kaehlcke: > > The USB PHY clock can be configured as (grand) parent of uart0_sclk and > > sclk_gpu. It has been observed that UART0 doesn't

Re: [PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-11 Thread Heiko Stübner
Hi Matthias, Am Donnerstag, 11. April 2019, 19:59:17 CEST schrieb Matthias Kaehlcke: > The USB PHY clock can be configured as (grand) parent of uart0_sclk and > sclk_gpu. It has been observed that UART0 doesn't work reliably in high > speed mode with the PHY clock as input when certain USB

[PATCH] clk: rockchip: rk3288: Limit use of USB PHY clock to USB

2019-04-11 Thread Matthias Kaehlcke
The USB PHY clock can be configured as (grand) parent of uart0_sclk and sclk_gpu. It has been observed that UART0 doesn't work reliably in high speed mode with the PHY clock as input when certain USB devices are plugged to the USB HOST1 port (see https://crrev.com/c/320543). Prefix the name of